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LearnGO/go/pkg/mod/golang.org/x/arch@v0.6.0/ppc64/pp64.csv
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2024-09-19 21:38:24 -04:00

143 KiB

1# POWER ISA 3.1B instruction description.
2#
3# This file contains comment lineseach beginning with #
4# followed by entries in CSV format.
5#
6# Each line in the CSV section contains 4 fields:
7#
8# instruction mnemonic encoding isa-level
9#
10# The instruction is the headline from the manual.
11# The mnemonic is the instruction mnemonicsseparated by | characters.
12# The encoding is the encodinga sequence of name@startbit| describing each bit field in turn or
13# a list of sequences of the form (sequence)+. A leading comma is used to signify an
14# instruction encoding requiring multiple instruction words.
15# The fourth field represents the ISA version where the instruction was introduced as
16# stated in Appendix F. of ISA 3.1B
17#
18Hash Check X-formhashchk RB,offset(RA)31@0|D@6|RA@11|RB@16|754@21|DX@31|v3.1B
19Hash Check Privileged X-formhashchkp RB,offset(RA)31@0|D@6|RA@11|RB@16|690@21|DX@31|v3.1B
20Hash Store X-formhashst RB,offset(RA)31@0|D@6|RA@11|RB@16|722@21|DX@31|v3.1B
21Hash Store Privileged X-formhashstp RB,offset(RA)31@0|D@6|RA@11|RB@16|658@21|DX@31|v3.1B
22Byte-Reverse Doubleword X-formbrd RA,RS31@0|RS@6|RA@11|///@16|187@21|/@31|v3.1
23Byte-Reverse Halfword X-formbrh RA,RS31@0|RS@6|RA@11|///@16|219@21|/@31|v3.1
24Byte-Reverse Word X-formbrw RA,RS31@0|RS@6|RA@11|///@16|155@21|/@31|v3.1
25Centrifuge Doubleword X-formcfuged RA,RS,RB31@0|RS@6|RA@11|RB@16|220@21|/@31|v3.1
26Count Leading Zeros Doubleword under bit Mask X-formcntlzdm RA,RS,RB31@0|RS@6|RA@11|RB@16|59@21|/@31|v3.1
27Count Trailing Zeros Doubleword under bit Mask X-formcnttzdm RA,RS,RB31@0|RS@6|RA@11|RB@16|571@21|/@31|v3.1
28DFP Convert From Fixed Quadword Quad X-formdcffixqq FRTp,VRB63@0|FRTp@6|0@11|VRB@16|994@21|/@31|v3.1
29DFP Convert To Fixed Quadword Quad X-formdctfixqq VRT,FRBp63@0|VRT@6|1@11|FRBp@16|994@21|/@31|v3.1
30Load VSX Vector Special Value Quadword X-formlxvkq XT,UIM60@0|T@6|31@11|UIM@16|360@21|TX@31|v3.1
31Load VSX Vector Paired DQ-formlxvp XTp,DQ(RA)6@0|Tp@6|TX@10|RA@11|DQ@16|0@28|v3.1
32Load VSX Vector Paired Indexed X-formlxvpx XTp,RA,RB31@0|Tp@6|TX@10|RA@11|RB@16|333@21|/@31|v3.1
33Load VSX Vector Rightmost Byte Indexed X-formlxvrbx XT,RA,RB31@0|T@6|RA@11|RB@16|13@21|TX@31|v3.1
34Load VSX Vector Rightmost Doubleword Indexed X-formlxvrdx XT,RA,RB31@0|T@6|RA@11|RB@16|109@21|TX@31|v3.1
35Load VSX Vector Rightmost Halfword Indexed X-formlxvrhx XT,RA,RB31@0|T@6|RA@11|RB@16|45@21|TX@31|v3.1
36Load VSX Vector Rightmost Word Indexed X-formlxvrwx XT,RA,RB31@0|T@6|RA@11|RB@16|77@21|TX@31|v3.1
37Move to VSR Byte Mask VX-formmtvsrbm VRT,RB4@0|VRT@6|16@11|RB@16|1602@21|v3.1
38Move To VSR Byte Mask Immediate DX-formmtvsrbmi VRT,bm4@0|VRT@6|b1@11|b0@16|10@26|b2@31|v3.1
39Move to VSR Doubleword Mask VX-formmtvsrdm VRT,RB4@0|VRT@6|19@11|RB@16|1602@21|v3.1
40Move to VSR Halfword Mask VX-formmtvsrhm VRT,RB4@0|VRT@6|17@11|RB@16|1602@21|v3.1
41Move to VSR Quadword Mask VX-formmtvsrqm VRT,RB4@0|VRT@6|20@11|RB@16|1602@21|v3.1
42Move to VSR Word Mask VX-formmtvsrwm VRT,RB4@0|VRT@6|18@11|RB@16|1602@21|v3.1
43Prefixed Add Immediate MLS:D-formpaddi RT,RA,SI,R,1@0|2@6|0@8|//@9|R@11|//@12|si0@14|,14@0|RT@6|RA@11|si1@16|v3.1
44Parallel Bits Deposit Doubleword X-formpdepd RA,RS,RB31@0|RS@6|RA@11|RB@16|156@21|/@31|v3.1
45Parallel Bits Extract Doubleword X-formpextd RA,RS,RB31@0|RS@6|RA@11|RB@16|188@21|/@31|v3.1
46Prefixed Load Byte and Zero MLS:D-formplbz RT,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,34@0|RT@6|RA@11|d1@16|v3.1
47Prefixed Load Doubleword 8LS:D-formpld RT,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,57@0|RT@6|RA@11|d1@16|v3.1
48Prefixed Load Floating-Point Double MLS:D-formplfd FRT,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,50@0|FRT@6|RA@11|d1@16|v3.1
49Prefixed Load Floating-Point Single MLS:D-formplfs FRT,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,48@0|FRT@6|RA@11|d1@16|v3.1
50Prefixed Load Halfword Algebraic MLS:D-formplha RT,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,42@0|RT@6|RA@11|d1@16|v3.1
51Prefixed Load Halfword and Zero MLS:D-formplhz RT,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,40@0|RT@6|RA@11|d1@16|v3.1
52Prefixed Load Quadword 8LS:D-formplq RTp,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,56@0|RTp@6|RA@11|d1@16|v3.1
53Prefixed Load Word Algebraic 8LS:D-formplwa RT,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,41@0|RT@6|RA@11|d1@16|v3.1
54Prefixed Load Word and Zero MLS:D-formplwz RT,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,32@0|RT@6|RA@11|d1@16|v3.1
55Prefixed Load VSX Scalar Doubleword 8LS:D-formplxsd VRT,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,42@0|VRT@6|RA@11|d1@16|v3.1
56Prefixed Load VSX Scalar Single-Precision 8LS:D-formplxssp VRT,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,43@0|VRT@6|RA@11|d1@16|v3.1
57Prefixed Load VSX Vector 8LS:D-formplxv XT,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,25@0|TX@5|T@6|RA@11|d1@16|v3.1
58Prefixed Load VSX Vector Paired 8LS:D-formplxvp XTp,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,58@0|Tp@6|TX@10|RA@11|d1@16|v3.1
59Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) MMIRR:XX3-formpmxvbf16ger2 AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|51@21|AX@29|BX@30|/@31|v3.1
60Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate MMIRR:XX3-formpmxvbf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|242@21|AX@29|BX@30|/@31|v3.1
61Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate MMIRR:XX3-formpmxvbf16ger2np AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|114@21|AX@29|BX@30|/@31|v3.1
62Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate MMIRR:XX3-formpmxvbf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|178@21|AX@29|BX@30|/@31|v3.1
63Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate MMIRR:XX3-formpmxvbf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|50@21|AX@29|BX@30|/@31|v3.1
64Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) MMIRR:XX3-formpmxvf16ger2 AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|19@21|AX@29|BX@30|/@31|v3.1
65Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate MMIRR:XX3-formpmxvf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|210@21|AX@29|BX@30|/@31|v3.1
66Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate MMIRR:XX3-formpmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|82@21|AX@29|BX@30|/@31|v3.1
67Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate MMIRR:XX3-formpmxvf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|146@21|AX@29|BX@30|/@31|v3.1
68Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-formpmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|18@21|AX@29|BX@30|/@31|v3.1
69Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) MMIRR:XX3-formpmxvf32ger AT,XA,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|27@21|AX@29|BX@30|/@31|v3.1
70Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-formpmxvf32gernn AT,XA,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|218@21|AX@29|BX@30|/@31|v3.1
71Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-formpmxvf32gernp AT,XA,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|90@21|AX@29|BX@30|/@31|v3.1
72Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-formpmxvf32gerpn AT,XA,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|154@21|AX@29|BX@30|/@31|v3.1
73Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-formpmxvf32gerpp AT,XA,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|26@21|AX@29|BX@30|/@31|v3.1
74Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) MMIRR:XX3-formpmxvf64ger AT,XAp,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|59@21|AX@29|BX@30|/@31|v3.1
75Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-formpmxvf64gernn AT,XAp,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|250@21|AX@29|BX@30|/@31|v3.1
76Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-formpmxvf64gernp AT,XAp,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|122@21|AX@29|BX@30|/@31|v3.1
77Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-formpmxvf64gerpn AT,XAp,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|186@21|AX@29|BX@30|/@31|v3.1
78Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-formpmxvf64gerpp AT,XAp,XB,XMSK,YMSK,1@0|3@6|9@8|//@12|/@14|/@15|///@16|XMSK@24|YMSK@28|//@30|,59@0|AT@6|//@9|Ap@11|B@16|58@21|AX@29|BX@30|/@31|v3.1
79Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) MMIRR:XX3-formpmxvi16ger2 AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|75@21|AX@29|BX@30|/@31|v3.1
80Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-formpmxvi16ger2pp AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|107@21|AX@29|BX@30|/@31|v3.1
81Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation MMIRR:XX3-formpmxvi16ger2s AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|43@21|AX@29|BX@30|/@31|v3.1
82Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate MMIRR:XX3-formpmxvi16ger2spp AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@18|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|42@21|AX@29|BX@30|/@31|v3.1
83Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) MMIRR:XX3-formpmxvi4ger8 AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|35@21|AX@29|BX@30|/@31|v3.1
84Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate MMIRR:XX3-formpmxvi4ger8pp AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|34@21|AX@29|BX@30|/@31|v3.1
85Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) MMIRR:XX3-formpmxvi8ger4 AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@20|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|3@21|AX@29|BX@30|/@31|v3.1
86Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate MMIRR:XX3-formpmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@20|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|2@21|AX@29|BX@30|/@31|v3.1
87Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate MMIRR:XX3-formpmxvi8ger4spp AT,XA,XB,XMSK,YMSK,PMSK,1@0|3@6|9@8|//@12|/@14|/@15|PMSK@16|///@20|XMSK@24|YMSK@28|,59@0|AT@6|//@9|A@11|B@16|99@21|AX@29|BX@30|/@31|v3.1
88Prefixed Nop MRR:*-formpnop,1@0|3@6|0@8|///@12|0@14|//@31|,///@0|v3.1
89Prefixed Store Byte MLS:D-formpstb RS,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,38@0|RS@6|RA@11|d1@16|v3.1
90Prefixed Store Doubleword 8LS:D-formpstd RS,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,61@0|RS@6|RA@11|d1@16|v3.1
91Prefixed Store Floating-Point Double MLS:D-formpstfd FRS,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,54@0|FRS@6|RA@11|d1@16|v3.1
92Prefixed Store Floating-Point Single MLS:D-formpstfs FRS,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,52@0|FRS@6|RA@11|d1@16|v3.1
93Prefixed Store Halfword MLS:D-formpsth RS,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,44@0|RS@6|RA@11|d1@16|v3.1
94Prefixed Store Quadword 8LS:D-formpstq RSp,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,60@0|RSp@6|RA@11|d1@16|v3.1
95Prefixed Store Word MLS:D-formpstw RS,D(RA),R,1@0|2@6|0@8|//@9|R@11|//@12|d0@14|,36@0|RS@6|RA@11|d1@16|v3.1
96Prefixed Store VSX Scalar Doubleword 8LS:D-formpstxsd VRS,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,46@0|VRS@6|RA@11|d1@16|v3.1
97Prefixed Store VSX Scalar Single-Precision 8LS:D-formpstxssp VRS,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,47@0|VRS@6|RA@11|d1@16|v3.1
98Prefixed Store VSX Vector 8LS:D-formpstxv XS,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,27@0|SX@5|S@6|RA@11|d1@16|v3.1
99Prefixed Store VSX Vector Paired 8LS:D-formpstxvp XSp,D(RA),R,1@0|0@6|0@8|//@9|R@11|//@12|d0@14|,62@0|Sp@6|SX@10|RA@11|d1@16|v3.1
100Set Boolean Condition X-formsetbc RT,BI31@0|RT@6|BI@11|///@16|384@21|/@31|v3.1
101Set Boolean Condition Reverse X-formsetbcr RT,BI31@0|RT@6|BI@11|///@16|416@21|/@31|v3.1
102Set Negative Boolean Condition X-formsetnbc RT,BI31@0|RT@6|BI@11|///@16|448@21|/@31|v3.1
103Set Negative Boolean Condition Reverse X-formsetnbcr RT,BI31@0|RT@6|BI@11|///@16|480@21|/@31|v3.1
104Store VSX Vector Paired DQ-formstxvp XSp,DQ(RA)6@0|Sp@6|SX@10|RA@11|DQ@16|1@28|v3.1
105Store VSX Vector Paired Indexed X-formstxvpx XSp,RA,RB31@0|Sp@6|SX@10|RA@11|RB@16|461@21|/@31|v3.1
106Store VSX Vector Rightmost Byte Indexed X-formstxvrbx XS,RA,RB31@0|S@6|RA@11|RB@16|141@21|SX@31|v3.1
107Store VSX Vector Rightmost Doubleword Indexed X-formstxvrdx XS,RA,RB31@0|S@6|RA@11|RB@16|237@21|SX@31|v3.1
108Store VSX Vector Rightmost Halfword Indexed X-formstxvrhx XS,RA,RB31@0|S@6|RA@11|RB@16|173@21|SX@31|v3.1
109Store VSX Vector Rightmost Word Indexed X-formstxvrwx XS,RA,RB31@0|S@6|RA@11|RB@16|205@21|SX@31|v3.1
110Vector Centrifuge Doubleword VX-formvcfuged VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1357@21|v3.1
111Vector Clear Leftmost Bytes VX-formvclrlb VRT,VRA,RB4@0|VRT@6|VRA@11|RB@16|397@21|v3.1
112Vector Clear Rightmost Bytes VX-formvclrrb VRT,VRA,RB4@0|VRT@6|VRA@11|RB@16|461@21|v3.1
113Vector Count Leading Zeros Doubleword under bit Mask VX-formvclzdm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1924@21|v3.1
114Vector Compare Equal Quadword VC-formvcmpequq VRT,VRA,VRB (Rc=0)|vcmpequq. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|455@22|v3.1
115Vector Compare Greater Than Signed Quadword VC-formvcmpgtsq VRT,VRA,VRB (Rc=0)|vcmpgtsq. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|903@22|v3.1
116Vector Compare Greater Than Unsigned Quadword VC-formvcmpgtuq VRT,VRA,VRB (Rc=0)|vcmpgtuq. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|647@22|v3.1
117Vector Compare Signed Quadword VX-formvcmpsq BF,VRA,VRB4@0|BF@6|//@9|VRA@11|VRB@16|321@21|v3.1
118Vector Compare Unsigned Quadword VX-formvcmpuq BF,VRA,VRB4@0|BF@6|//@9|VRA@11|VRB@16|257@21|v3.1
119Vector Count Mask Bits Byte VX-formvcntmbb RT,VRB,MP4@0|RT@6|12@11|MP@15|VRB@16|1602@21|v3.1
120Vector Count Mask Bits Doubleword VX-formvcntmbd RT,VRB,MP4@0|RT@6|15@11|MP@15|VRB@16|1602@21|v3.1
121Vector Count Mask Bits Halfword VX-formvcntmbh RT,VRB,MP4@0|RT@6|13@11|MP@15|VRB@16|1602@21|v3.1
122Vector Count Mask Bits Word VX-formvcntmbw RT,VRB,MP4@0|RT@6|14@11|MP@15|VRB@16|1602@21|v3.1
123Vector Count Trailing Zeros Doubleword under bit Mask VX-formvctzdm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1988@21|v3.1
124Vector Divide Extended Signed Doubleword VX-formvdivesd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|971@21|v3.1
125Vector Divide Extended Signed Quadword VX-formvdivesq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|779@21|v3.1
126Vector Divide Extended Signed Word VX-formvdivesw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|907@21|v3.1
127Vector Divide Extended Unsigned Doubleword VX-formvdiveud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|715@21|v3.1
128Vector Divide Extended Unsigned Quadword VX-formvdiveuq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|523@21|v3.1
129Vector Divide Extended Unsigned Word VX-formvdiveuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|651@21|v3.1
130Vector Divide Signed Doubleword VX-formvdivsd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|459@21|v3.1
131Vector Divide Signed Quadword VX-formvdivsq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|267@21|v3.1
132Vector Divide Signed Word VX-formvdivsw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|395@21|v3.1
133Vector Divide Unsigned Doubleword VX-formvdivud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|203@21|v3.1
134Vector Divide Unsigned Quadword VX-formvdivuq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|11@21|v3.1
135Vector Divide Unsigned Word VX-formvdivuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|139@21|v3.1
136Vector Expand Byte Mask VX-formvexpandbm VRT,VRB4@0|VRT@6|0@11|VRB@16|1602@21|v3.1
137Vector Expand Doubleword Mask VX-formvexpanddm VRT,VRB4@0|VRT@6|3@11|VRB@16|1602@21|v3.1
138Vector Expand Halfword Mask VX-formvexpandhm VRT,VRB4@0|VRT@6|1@11|VRB@16|1602@21|v3.1
139Vector Expand Quadword Mask VX-formvexpandqm VRT,VRB4@0|VRT@6|4@11|VRB@16|1602@21|v3.1
140Vector Expand Word Mask VX-formvexpandwm VRT,VRB4@0|VRT@6|2@11|VRB@16|1602@21|v3.1
141Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-formvextddvlx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|30@26|v3.1
142Vector Extract Double Doubleword to VSR using GPR-specified Right-Index VA-formvextddvrx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|31@26|v3.1
143Vector Extract Double Unsigned Byte to VSR using GPR-specified Left-Index VA-formvextdubvlx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|24@26|v3.1
144Vector Extract Double Unsigned Byte to VSR using GPR-specified Right-Index VA-formvextdubvrx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|25@26|v3.1
145Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-formvextduhvlx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|26@26|v3.1
146Vector Extract Double Unsigned Halfword to VSR using GPR-specified Right-Index VA-formvextduhvrx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|27@26|v3.1
147Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-formvextduwvlx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|28@26|v3.1
148Vector Extract Double Unsigned Word to VSR using GPR-specified Right-Index VA-formvextduwvrx VRT,VRA,VRB,RC4@0|VRT@6|VRA@11|VRB@16|RC@21|29@26|v3.1
149Vector Extract Byte Mask VX-formvextractbm RT,VRB4@0|RT@6|8@11|VRB@16|1602@21|v3.1
150Vector Extract Doubleword Mask VX-formvextractdm RT,VRB4@0|RT@6|11@11|VRB@16|1602@21|v3.1
151Vector Extract Halfword Mask VX-formvextracthm RT,VRB4@0|RT@6|9@11|VRB@16|1602@21|v3.1
152Vector Extract Quadword Mask VX-formvextractqm RT,VRB4@0|RT@6|12@11|VRB@16|1602@21|v3.1
153Vector Extract Word Mask VX-formvextractwm RT,VRB4@0|RT@6|10@11|VRB@16|1602@21|v3.1
154Vector Extend Sign Doubleword to Quadword VX-formvextsd2q VRT,VRB4@0|VRT@6|27@11|VRB@16|1538@21|v3.1
155Vector Gather every Nth Bit VX-formvgnb RT,VRB,N4@0|RT@6|//@11|N@13|VRB@16|1228@21|v3.1
156Vector Insert Byte from GPR using GPR-specified Left-Index VX-formvinsblx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|527@21|v3.1
157Vector Insert Byte from GPR using GPR-specified Right-Index VX-formvinsbrx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|783@21|v3.1
158Vector Insert Byte from VSR using GPR-specified Left-Index VX-formvinsbvlx VRT,RA,VRB4@0|VRT@6|RA@11|VRB@16|15@21|v3.1
159Vector Insert Byte from VSR using GPR-specified Right-Index VX-formvinsbvrx VRT,RA,VRB4@0|VRT@6|RA@11|VRB@16|271@21|v3.1
160Vector Insert Doubleword from GPR using immediate-specified index VX-formvinsd VRT,RB,UIM4@0|VRT@6|/@11|UIM@12|RB@16|463@21|v3.1
161Vector Insert Doubleword from GPR using GPR-specified Left-Index VX-formvinsdlx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|719@21|v3.1
162Vector Insert Doubleword from GPR using GPR-specified Right-Index VX-formvinsdrx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|975@21|v3.1
163Vector Insert Halfword from GPR using GPR-specified Left-Index VX-formvinshlx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|591@21|v3.1
164Vector Insert Halfword from GPR using GPR-specified Right-Index VX-formvinshrx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|847@21|v3.1
165Vector Insert Halfword from VSR using GPR-specified Left-Index VX-formvinshvlx VRT,RA,VRB4@0|VRT@6|RA@11|VRB@16|79@21|v3.1
166Vector Insert Halfword from VSR using GPR-specified Right-Index VX-formvinshvrx VRT,RA,VRB4@0|VRT@6|RA@11|VRB@16|335@21|v3.1
167Vector Insert Word from GPR using immediate-specified index VX-formvinsw VRT,RB,UIM4@0|VRT@6|/@11|UIM@12|RB@16|207@21|v3.1
168Vector Insert Word from GPR using GPR-specified Left-Index VX-formvinswlx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|655@21|v3.1
169Vector Insert Word from GPR using GPR-specified Right-Index VX-formvinswrx VRT,RA,RB4@0|VRT@6|RA@11|RB@16|911@21|v3.1
170Vector Insert Word from VSR using GPR-specified Left-Index VX-formvinswvlx VRT,RA,VRB4@0|VRT@6|RA@11|VRB@16|143@21|v3.1
171Vector Insert Word from VSR using GPR-specified Left-Index VX-formvinswvrx VRT,RA,VRB4@0|VRT@6|RA@11|VRB@16|399@21|v3.1
172Vector Modulo Signed Doubleword VX-formvmodsd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1995@21|v3.1
173Vector Modulo Signed Quadword VX-formvmodsq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1803@21|v3.1
174Vector Modulo Signed Word VX-formvmodsw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1931@21|v3.1
175Vector Modulo Unsigned Doubleword VX-formvmodud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1739@21|v3.1
176Vector Modulo Unsigned Quadword VX-formvmoduq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1547@21|v3.1
177Vector Modulo Unsigned Word VX-formvmoduw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1675@21|v3.1
178Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-formvmsumcud VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|23@26|v3.1
179Vector Multiply Even Signed Doubleword VX-formvmulesd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|968@21|v3.1
180Vector Multiply Even Unsigned Doubleword VX-formvmuleud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|712@21|v3.1
181Vector Multiply High Signed Doubleword VX-formvmulhsd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|969@21|v3.1
182Vector Multiply High Signed Word VX-formvmulhsw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|905@21|v3.1
183Vector Multiply High Unsigned Doubleword VX-formvmulhud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|713@21|v3.1
184Vector Multiply High Unsigned Word VX-formvmulhuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|649@21|v3.1
185Vector Multiply Low Doubleword VX-formvmulld VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|457@21|v3.1
186Vector Multiply Odd Signed Doubleword VX-formvmulosd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|456@21|v3.1
187Vector Multiply Odd Unsigned Doubleword VX-formvmuloud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|200@21|v3.1
188Vector Parallel Bits Deposit Doubleword VX-formvpdepd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1485@21|v3.1
189Vector Parallel Bits Extract Doubleword VX-formvpextd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1421@21|v3.1
190Vector Rotate Left Quadword VX-formvrlq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|5@21|v3.1
191Vector Rotate Left Quadword then Mask Insert VX-formvrlqmi VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|69@21|v3.1
192Vector Rotate Left Quadword then AND with Mask VX-formvrlqnm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|325@21|v3.1
193Vector Shift Left Double by Bit Immediate VN-formvsldbi VRT,VRA,VRB,SH4@0|VRT@6|VRA@11|VRB@16|0@21|SH@23|22@26|v3.1
194Vector Shift Left Quadword VX-formvslq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|261@21|v3.1
195Vector Shift Right Algebraic Quadword VX-formvsraq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|773@21|v3.1
196Vector Shift Right Double by Bit Immediate VN-formvsrdbi VRT,VRA,VRB,SH4@0|VRT@6|VRA@11|VRB@16|1@21|SH@23|22@26|v3.1
197Vector Shift Right Quadword VX-formvsrq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|517@21|v3.1
198Vector String Isolate Byte Left-justified VX-formvstribl VRT,VRB (Rc=0)|vstribl. VRT,VRB (Rc=1)4@0|VRT@6|0@11|VRB@16|Rc@21|13@22|v3.1
199Vector String Isolate Byte Right-justified VX-formvstribr VRT,VRB (Rc=0)|vstribr. VRT,VRB (Rc=1)4@0|VRT@6|1@11|VRB@16|Rc@21|13@22|v3.1
200Vector String Isolate Halfword Left-justified VX-formvstrihl VRT,VRB (Rc=0)|vstrihl. VRT,VRB (Rc=1)4@0|VRT@6|2@11|VRB@16|Rc@21|13@22|v3.1
201Vector String Isolate Halfword Right-justified VX-formvstrihr VRT,VRB (Rc=0)|vstrihr. VRT,VRB (Rc=1)4@0|VRT@6|3@11|VRB@16|Rc@21|13@22|v3.1
202VSX Scalar Compare Equal Quad-Precision X-formxscmpeqqp VRT,VRA,VRB63@0|VRT@6|VRA@11|VRB@16|68@21|/@31|v3.1
203VSX Scalar Compare Greater Than or Equal Quad-Precision X-formxscmpgeqp VRT,VRA,VRB63@0|VRT@6|VRA@11|VRB@16|196@21|/@31|v3.1
204VSX Scalar Compare Greater Than Quad-Precision X-formxscmpgtqp VRT,VRA,VRB63@0|VRT@6|VRA@11|VRB@16|228@21|/@31|v3.1
205VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword X-formxscvqpsqz VRT,VRB63@0|VRT@6|8@11|VRB@16|836@21|/@31|v3.1
206VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword X-formxscvqpuqz VRT,VRB63@0|VRT@6|0@11|VRB@16|836@21|/@31|v3.1
207VSX Scalar Convert with round Signed Quadword to Quad-Precision X-formxscvsqqp VRT,VRB63@0|VRT@6|11@11|VRB@16|836@21|/@31|v3.1
208VSX Scalar Convert with round Unsigned Quadword to Quad-Precision X-formxscvuqqp VRT,VRB63@0|VRT@6|3@11|VRB@16|836@21|/@31|v3.1
209VSX Scalar Maximum Type-C Quad-Precision X-formxsmaxcqp VRT,VRA,VRB63@0|VRT@6|VRA@11|VRB@16|676@21|/@31|v3.1
210VSX Scalar Minimum Type-C Quad-Precision X-formxsmincqp VRT,VRA,VRB63@0|VRT@6|VRA@11|VRB@16|740@21|/@31|v3.1
211VSX Vector bfloat16 GER (Rank-2 Update) XX3-formxvbf16ger2 AT,XA,XB59@0|AT@6|//@9|A@11|B@16|51@21|AX@29|BX@30|/@31|v3.1
212VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate XX3-formxvbf16ger2nn AT,XA,XB59@0|AT@6|//@9|A@11|B@16|242@21|AX@29|BX@30|/@31|v3.1
213VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate XX3-formxvbf16ger2np AT,XA,XB59@0|AT@6|//@9|A@11|B@16|114@21|AX@29|BX@30|/@31|v3.1
214VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate XX3-formxvbf16ger2pn AT,XA,XB59@0|AT@6|//@9|A@11|B@16|178@21|AX@29|BX@30|/@31|v3.1
215VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate XX3-formxvbf16ger2pp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|50@21|AX@29|BX@30|/@31|v3.1
216VSX Vector Convert bfloat16 to Single-Precision format Non-signaling XX2-formxvcvbf16spn XT,XB60@0|T@6|16@11|B@16|475@21|BX@30|TX@31|v3.1
217VSX Vector Convert with round Single-Precision to bfloat16 format XX2-formxvcvspbf16 XT,XB60@0|T@6|17@11|B@16|475@21|BX@30|TX@31|v3.1
218VSX Vector 16-bit Floating-Point GER (rank-2 update) XX3-formxvf16ger2 AT,XA,XB59@0|AT@6|//@9|A@11|B@16|19@21|AX@29|BX@30|/@31|v3.1
219VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate XX3-formxvf16ger2nn AT,XA,XB59@0|AT@6|//@9|A@11|B@16|210@21|AX@29|BX@30|/@31|v3.1
220VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate XX3-formxvf16ger2np AT,XA,XB59@0|AT@6|//@9|A@11|B@16|82@21|AX@29|BX@30|/@31|v3.1
221VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate XX3-formxvf16ger2pn AT,XA,XB59@0|AT@6|//@9|A@11|B@16|146@21|AX@29|BX@30|/@31|v3.1
222VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate XX3-formxvf16ger2pp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|18@21|AX@29|BX@30|/@31|v3.1
223VSX Vector 32-bit Floating-Point GER (rank-1 update) XX3-formxvf32ger AT,XA,XB59@0|AT@6|//@9|A@11|B@16|27@21|AX@29|BX@30|/@31|v3.1
224VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-formxvf32gernn AT,XA,XB59@0|AT@6|//@9|A@11|B@16|218@21|AX@29|BX@30|/@31|v3.1
225VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-formxvf32gernp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|90@21|AX@29|BX@30|/@31|v3.1
226VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-formxvf32gerpn AT,XA,XB59@0|AT@6|//@9|A@11|B@16|154@21|AX@29|BX@30|/@31|v3.1
227VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-formxvf32gerpp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|26@21|AX@29|BX@30|/@31|v3.1
228VSX Vector 64-bit Floating-Point GER (rank-1 update) XX3-formxvf64ger AT,XAp,XB59@0|AT@6|//@9|Ap@11|B@16|59@21|AX@29|BX@30|/@31|v3.1
229VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-formxvf64gernn AT,XAp,XB59@0|AT@6|//@9|Ap@11|B@16|250@21|AX@29|BX@30|/@31|v3.1
230VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-formxvf64gernp AT,XAp,XB59@0|AT@6|//@9|Ap@11|B@16|122@21|AX@29|BX@30|/@31|v3.1
231VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-formxvf64gerpn AT,XAp,XB59@0|AT@6|//@9|Ap@11|B@16|186@21|AX@29|BX@30|/@31|v3.1
232VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-formxvf64gerpp AT,XAp,XB59@0|AT@6|//@9|Ap@11|B@16|58@21|AX@29|BX@30|/@31|v3.1
233VSX Vector 16-bit Signed Integer GER (rank-2 update) XX3-formxvi16ger2 AT,XA,XB59@0|AT@6|//@9|A@11|B@16|75@21|AX@29|BX@30|/@31|v3.1
234VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate XX3-formxvi16ger2pp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|107@21|AX@29|BX@30|/@31|v3.1
235VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation XX3-formxvi16ger2s AT,XA,XB59@0|AT@6|//@9|A@11|B@16|43@21|AX@29|BX@30|/@31|v3.1
236VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate XX3-formxvi16ger2spp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|42@21|AX@29|BX@30|/@31|v3.1
237VSX Vector 4-bit Signed Integer GER (rank-8 update) XX3-formxvi4ger8 AT,XA,XB59@0|AT@6|//@9|A@11|B@16|35@21|AX@29|BX@30|/@31|v3.1
238VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate XX3-formxvi4ger8pp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|34@21|AX@29|BX@30|/@31|v3.1
239VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) XX3-formxvi8ger4 AT,XA,XB59@0|AT@6|//@9|A@11|B@16|3@21|AX@29|BX@30|/@31|v3.1
240VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate XX3-formxvi8ger4pp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|2@21|AX@29|BX@30|/@31|v3.1
241VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate XX3-formxvi8ger4spp AT,XA,XB59@0|AT@6|//@9|A@11|B@16|99@21|AX@29|BX@30|/@31|v3.1
242VSX Vector Test Least-Significant Bit by Byte XX2-formxvtlsbb BF,XB60@0|BF@6|//@9|2@11|B@16|475@21|BX@30|/@31|v3.1
243VSX Vector Blend Variable Byte 8RR:XX4-formxxblendvb XT,XA,XB,XC,1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|0@26|CX@28|AX@29|BX@30|TX@31|v3.1
244VSX Vector Blend Variable Doubleword 8RR:XX4-formxxblendvd XT,XA,XB,XC,1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|v3.1
245VSX Vector Blend Variable Halfword 8RR:XX4-formxxblendvh XT,XA,XB,XC,1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|1@26|CX@28|AX@29|BX@30|TX@31|v3.1
246VSX Vector Blend Variable Word 8RR:XX4-formxxblendvw XT,XA,XB,XC,1@0|1@6|0@8|//@12|///@14|,33@0|T@6|A@11|B@16|C@21|2@26|CX@28|AX@29|BX@30|TX@31|v3.1
247VSX Vector Evaluate 8RR-XX4-formxxeval XT,XA,XB,XC,IMM,1@0|1@6|0@8|//@12|///@14|IMM@24|,34@0|T@6|A@11|B@16|C@21|1@26|CX@28|AX@29|BX@30|TX@31|v3.1
248VSX Vector Generate PCV from Byte Mask X-formxxgenpcvbm XT,VRB,IMM60@0|T@6|IMM@11|VRB@16|916@21|TX@31|v3.1
249VSX Vector Generate PCV from Doubleword Mask X-formxxgenpcvdm XT,VRB,IMM60@0|T@6|IMM@11|VRB@16|949@21|TX@31|v3.1
250VSX Vector Generate PCV from Halfword Mask X-formxxgenpcvhm XT,VRB,IMM60@0|T@6|IMM@11|VRB@16|917@21|TX@31|v3.1
251VSX Vector Generate PCV from Word Mask X-formxxgenpcvwm XT,VRB,IMM60@0|T@6|IMM@11|VRB@16|948@21|TX@31|v3.1
252VSX Move From Accumulator X-formxxmfacc AS31@0|AS@6|//@9|0@11|///@16|177@21|/@31|v3.1
253VSX Move To Accumulator X-formxxmtacc AT31@0|AT@6|//@9|1@11|///@16|177@21|/@31|v3.1
254VSX Vector Permute Extended 8RR:XX4-formxxpermx XT,XA,XB,XC,UIM,1@0|1@6|0@8|//@12|///@14|UIM@29|,34@0|T@6|A@11|B@16|C@21|0@26|CX@28|AX@29|BX@30|TX@31|v3.1
255VSX Set Accumulator to Zero X-formxxsetaccz AT31@0|AT@6|//@9|3@11|///@16|177@21|/@31|v3.1
256VSX Vector Splat Immediate32 Doubleword Indexed 8RR:D-formxxsplti32dx XT,IX,IMM32,1@0|1@6|0@8|//@12|//@14|imm0@16|,32@0|T@6|0@11|IX@14|TX@15|imm1@16|v3.1
257VSX Vector Splat Immediate Double-Precision 8RR:D-formxxspltidp XT,IMM32,1@0|1@6|0@8|//@12|//@14|imm0@16|,32@0|T@6|2@11|TX@15|imm1@16|v3.1
258VSX Vector Splat Immediate Word 8RR:D-formxxspltiw XT,IMM32,1@0|1@6|0@8|//@12|//@14|imm0@16|,32@0|T@6|3@11|TX@15|imm1@16|v3.1
259Ultravisor Message Clear X-formmsgclru RB31@0|///@6|///@11|RB@16|110@21|/@31|v3.0C
260Ultravisor Message SendX-formmsgsndu RB31@0|///@6|///@11|RB@16|78@21|/@31|v3.0C
261Ultravisor Return From Interrupt Doubleword XL-formurfid19@0|///@6|///@11|///@16|306@21|/@31|v3.0C
262Add Extended using alternate carry bit Z23-formaddex RT,RA,RB,CY31@0|RT@6|RA@11|RB@16|CY@21|170@23|/@31|v3.0B
263Move From FPSCR Control & Set DRN X-formmffscdrn FRT,FRB63@0|FRT@6|20@11|FRB@16|583@21|/@31|v3.0B
264Move From FPSCR Control & Set DRN Immediate X-formmffscdrni FRT,DRM63@0|FRT@6|21@11|//@16|DRM@18|583@21|/@31|v3.0B
265Move From FPSCR & Clear Enables X-formmffsce FRT63@0|FRT@6|1@11|///@16|583@21|/@31|v3.0B
266Move From FPSCR Control & Set RN X-formmffscrn FRT,FRB63@0|FRT@6|22@11|FRB@16|583@21|/@31|v3.0B
267Move From FPSCR Control & Set RN Immediate X-formmffscrni FRT,RM63@0|FRT@6|23@11|///@16|RM@19|583@21|/@31|v3.0B
268Move From FPSCR Lightweight X-formmffsl FRT63@0|FRT@6|24@11|///@16|583@21|/@31|v3.0B
269SLB Invalidate All Global X-formslbiag RS, L31@0|RS@6|///@11|L@15|///@16|850@21|/@31|v3.0B
270Vector Multiply-Sum Unsigned Doubleword Modulo VA-formvmsumudm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|35@26|v3.0B
271Add PC Immediate Shifted DX-formaddpcis RT,D19@0|RT@6|d1@11|d0@16|2@26|d2@31|v3.0
272Decimal Convert From National VX-formbcdcfn. VRT,VRB,PS4@0|VRT@6|7@11|VRB@16|1@21|PS@22|385@23|v3.0
273Decimal Convert From Signed Quadword VX-formbcdcfsq. VRT,VRB,PS4@0|VRT@6|2@11|VRB@16|1@21|PS@22|385@23|v3.0
274Decimal Convert From Zoned VX-formbcdcfz. VRT,VRB,PS4@0|VRT@6|6@11|VRB@16|1@21|PS@22|385@23|v3.0
275Decimal Copy Sign VX-formbcdcpsgn. VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|833@21|v3.0
276Decimal Convert To National VX-formbcdctn. VRT,VRB4@0|VRT@6|5@11|VRB@16|1@21|/@22|385@23|v3.0
277Decimal Convert To Signed Quadword VX-formbcdctsq. VRT,VRB4@0|VRT@6|0@11|VRB@16|1@21|/@22|385@23|v3.0
278Decimal Convert To Zoned VX-formbcdctz. VRT,VRB,PS4@0|VRT@6|4@11|VRB@16|1@21|PS@22|385@23|v3.0
279Decimal Shift VX-formbcds. VRT,VRA,VRB,PS4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|193@23|v3.0
280Decimal Set Sign VX-formbcdsetsgn. VRT,VRB,PS4@0|VRT@6|31@11|VRB@16|1@21|PS@22|385@23|v3.0
281Decimal Shift and Round VX-formbcdsr. VRT,VRA,VRB,PS4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|449@23|v3.0
282Decimal Truncate VX-formbcdtrunc. VRT,VRA,VRB,PS4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|257@23|v3.0
283Decimal Unsigned Shift VX-formbcdus. VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1@21|/@22|129@23|v3.0
284Decimal Unsigned Truncate VX-formbcdutrunc. VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1@21|/@22|321@23|v3.0
285Compare Equal Byte X-formcmpeqb BF,RA,RB31@0|BF@6|//@9|RA@11|RB@16|224@21|/@31|v3.0
286Compare Ranged Byte X-formcmprb BF,L,RA,RB31@0|BF@6|/@9|L@10|RA@11|RB@16|192@21|/@31|v3.0
287Count Trailing Zeros Doubleword X-formcnttzd RA,RS (Rc=0)|cnttzd. RA,RS (Rc=1)31@0|RS@6|RA@11|///@16|570@21|Rc@31|v3.0
288Count Trailing Zeros Word X-formcnttzw RA,RS (Rc=0)|cnttzw. RA,RS (Rc=1)31@0|RS@6|RA@11|///@16|538@21|Rc@31|v3.0
289Copy X-formcopy RA,RB31@0|///@6|1@10|RA@11|RB@16|774@21|/@31|v3.0
290Copy-Paste Abort X-formcpabort31@0|///@6|///@11|///@16|838@21|/@31|v3.0
291Deliver A Random Number X-formdarn RT,L31@0|RT@6|///@11|L@14|///@16|755@21|/@31|v3.0
292DFP Test Significance Immediate X-formdtstsfi BF,UIM,FRB59@0|BF@6|/@9|UIM@10|FRB@16|675@21|/@31|v3.0
293DFP Test Significance Immediate Quad X-formdtstsfiq BF,UIM,FRBp63@0|BF@6|/@9|UIM@10|FRBp@16|675@21|/@31|v3.0
294Extend Sign Word and Shift Left Immediate XS-formextswsli RA,RS,SH (Rc=0)|extswsli. RA,RS,SH (Rc=1)31@0|RS@6|RA@11|sh@16|445@21|sh@30|Rc@31|v3.0
295Load Doubleword ATomic X-formldat RT,RA,FC31@0|RT@6|RA@11|FC@16|614@21|/@31|v3.0
296Load Word ATomic X-formlwat RT,RA,FC31@0|RT@6|RA@11|FC@16|582@21|/@31|v3.0
297Load VSX Scalar Doubleword DS-formlxsd VRT,DS(RA)57@0|VRT@6|RA@11|DS@16|2@30|v3.0
298Load VSX Scalar as Integer Byte & Zero Indexed X-formlxsibzx XT,RA,RB31@0|T@6|RA@11|RB@16|781@21|TX@31|v3.0
299Load VSX Scalar as Integer Halfword & Zero Indexed X-formlxsihzx XT,RA,RB31@0|T@6|RA@11|RB@16|813@21|TX@31|v3.0
300Load VSX Scalar Single-Precision DS-formlxssp VRT,DS(RA)57@0|VRT@6|RA@11|DS@16|3@30|v3.0
301Load VSX Vector DQ-formlxv XT,DQ(RA)61@0|T@6|RA@11|DQ@16|TX@28|1@29|v3.0
302Load VSX Vector Byte*16 Indexed X-formlxvb16x XT,RA,RB31@0|T@6|RA@11|RB@16|876@21|TX@31|v3.0
303Load VSX Vector Halfword*8 Indexed X-formlxvh8x XT,RA,RB31@0|T@6|RA@11|RB@16|812@21|TX@31|v3.0
304Load VSX Vector with Length X-formlxvl XT,RA,RB31@0|T@6|RA@11|RB@16|269@21|TX@31|v3.0
305Load VSX Vector with Length Left-justified X-formlxvll XT,RA,RB31@0|T@6|RA@11|RB@16|301@21|TX@31|v3.0
306Load VSX Vector Word & Splat Indexed X-formlxvwsx XT,RA,RB31@0|T@6|RA@11|RB@16|364@21|TX@31|v3.0
307Load VSX Vector Indexed X-formlxvx XT,RA,RB31@0|T@6|RA@11|RB@16|4@21|/@25|12@26|TX@31|v3.0
308Multiply-Add High Doubleword VA-formmaddhd RT,RA,RB,RC4@0|RT@6|RA@11|RB@16|RC@21|48@26|v3.0
309Multiply-Add High Doubleword Unsigned VA-formmaddhdu RT,RA,RB,RC4@0|RT@6|RA@11|RB@16|RC@21|49@26|v3.0
310Multiply-Add Low Doubleword VA-formmaddld RT,RA,RB,RC4@0|RT@6|RA@11|RB@16|RC@21|51@26|v3.0
311Move to CR from XER Extended X-formmcrxrx BF31@0|BF@6|//@9|///@11|///@16|576@21|/@31|v3.0
312Move From VSR Lower Doubleword X-formmfvsrld RA,XS31@0|S@6|RA@11|///@16|307@21|SX@31|v3.0
313Modulo Signed Doubleword X-formmodsd RT,RA,RB31@0|RT@6|RA@11|RB@16|777@21|/@31|v3.0
314Modulo Signed Word X-formmodsw RT,RA,RB31@0|RT@6|RA@11|RB@16|779@21|/@31|v3.0
315Modulo Unsigned Doubleword X-formmodud RT,RA,RB31@0|RT@6|RA@11|RB@16|265@21|/@31|v3.0
316Modulo Unsigned Word X-formmoduw RT,RA,RB31@0|RT@6|RA@11|RB@16|267@21|/@31|v3.0
317Message Synchronize X-formmsgsync31@0|///@6|///@11|///@16|886@21|/@31|v3.0
318Move To VSR Double Doubleword X-formmtvsrdd XT,RA,RB31@0|T@6|RA@11|RB@16|435@21|TX@31|v3.0
319Move To VSR Word & Splat X-formmtvsrws XT,RA31@0|T@6|RA@11|///@16|403@21|TX@31|v3.0
320Paste X-formpaste. RA,RB,L31@0|///@6|L@10|RA@11|RB@16|902@21|1@31|v3.0
321Set Boolean X-formsetb RT,BFA31@0|RT@6|BFA@11|//@14|///@16|128@21|/@31|v3.0
322SLB Invalidate Entry Global X-formslbieg RS,RB31@0|RS@6|///@11|RB@16|466@21|/@31|v3.0
323SLB Synchronize X-formslbsync31@0|///@6|///@11|///@16|338@21|/@31|v3.0
324Store Doubleword ATomic X-formstdat RS,RA,FC31@0|RS@6|RA@11|FC@16|742@21|/@31|v3.0
325Stop XL-formstop19@0|///@6|///@11|///@16|370@21|/@31|v3.0
326Store Word ATomic X-formstwat RS,RA,FC31@0|RS@6|RA@11|FC@16|710@21|/@31|v3.0
327Store VSX Scalar Doubleword DS-formstxsd VRS,DS(RA)61@0|VRS@6|RA@11|DS@16|2@30|v3.0
328Store VSX Scalar as Integer Byte Indexed X-formstxsibx XS,RA,RB31@0|S@6|RA@11|RB@16|909@21|SX@31|v3.0
329Store VSX Scalar as Integer Halfword Indexed X-formstxsihx XS,RA,RB31@0|S@6|RA@11|RB@16|941@21|SX@31|v3.0
330Store VSX Scalar Single DS-formstxssp VRS,DS(RA)61@0|VRS@6|RA@11|DS@16|3@30|v3.0
331Store VSX Vector DQ-formstxv XS,DQ(RA)61@0|S@6|RA@11|DQ@16|SX@28|5@29|v3.0
332Store VSX Vector Byte*16 Indexed X-formstxvb16x XS,RA,RB31@0|S@6|RA@11|RB@16|1004@21|SX@31|v3.0
333Store VSX Vector Halfword*8 Indexed X-formstxvh8x XS,RA,RB31@0|S@6|RA@11|RB@16|940@21|SX@31|v3.0
334Store VSX Vector with Length X-formstxvl XS,RA,RB31@0|S@6|RA@11|RB@16|397@21|SX@31|v3.0
335Store VSX Vector with Length Left-justified X-formstxvll XS,RA,RB31@0|S@6|RA@11|RB@16|429@21|SX@31|v3.0
336Store VSX Vector Indexed X-formstxvx XS,RA,RB31@0|S@6|RA@11|RB@16|396@21|SX@31|v3.0
337Vector Absolute Difference Unsigned Byte VX-formvabsdub VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1027@21|v3.0
338Vector Absolute Difference Unsigned Halfword VX-formvabsduh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1091@21|v3.0
339Vector Absolute Difference Unsigned Word VX-formvabsduw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1155@21|v3.0
340Vector Bit Permute Doubleword VX-formvbpermd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1484@21|v3.0
341Vector Count Leading Zero Least-Significant Bits Byte VX-formvclzlsbb RT,VRB4@0|RT@6|0@11|VRB@16|1538@21|v3.0
342Vector Compare Not Equal Byte VC-formvcmpneb VRT,VRA,VRB (Rc=0)|vcmpneb. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|7@22|v3.0
343Vector Compare Not Equal Halfword VC-formvcmpneh VRT,VRA,VRB (Rc=0)|vcmpneh. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|71@22|v3.0
344Vector Compare Not Equal Word VC-formvcmpnew VRT,VRA,VRB (Rc=0)|vcmpnew. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|135@22|v3.0
345Vector Compare Not Equal or Zero Byte VC-formvcmpnezb VRT,VRA,VRB (Rc=0)|vcmpnezb. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|263@22|v3.0
346Vector Compare Not Equal or Zero Halfword VC-formvcmpnezh VRT,VRA,VRB (Rc=0)|vcmpnezh. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|327@22|v3.0
347Vector Compare Not Equal or Zero Word VC-formvcmpnezw VRT,VRA,VRB (Rc=0)|vcmpnezw. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|391@22|v3.0
348Vector Count Trailing Zeros Byte VX-formvctzb VRT,VRB4@0|VRT@6|28@11|VRB@16|1538@21|v3.0
349Vector Count Trailing Zeros Doubleword VX-formvctzd VRT,VRB4@0|VRT@6|31@11|VRB@16|1538@21|v3.0
350Vector Count Trailing Zeros Halfword VX-formvctzh VRT,VRB4@0|VRT@6|29@11|VRB@16|1538@21|v3.0
351Vector Count Trailing Zero Least-Significant Bits Byte VX-formvctzlsbb RT,VRB4@0|RT@6|1@11|VRB@16|1538@21|v3.0
352Vector Count Trailing Zeros Word VX-formvctzw VRT,VRB4@0|VRT@6|30@11|VRB@16|1538@21|v3.0
353Vector Extract Doubleword to VSR using immediate-specified index VX-formvextractd VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|717@21|v3.0
354Vector Extract Unsigned Byte to VSR using immediate-specified index VX-formvextractub VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|525@21|v3.0
355Vector Extract Unsigned Halfword to VSR using immediate-specified index VX-formvextractuh VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|589@21|v3.0
356Vector Extract Unsigned Word to VSR using immediate-specified index VX-formvextractuw VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|653@21|v3.0
357Vector Extend Sign Byte To Doubleword VX-formvextsb2d VRT,VRB4@0|VRT@6|24@11|VRB@16|1538@21|v3.0
358Vector Extend Sign Byte To Word VX-formvextsb2w VRT,VRB4@0|VRT@6|16@11|VRB@16|1538@21|v3.0
359Vector Extend Sign Halfword To Doubleword VX-formvextsh2d VRT,VRB4@0|VRT@6|25@11|VRB@16|1538@21|v3.0
360Vector Extend Sign Halfword To Word VX-formvextsh2w VRT,VRB4@0|VRT@6|17@11|VRB@16|1538@21|v3.0
361Vector Extend Sign Word To Doubleword VX-formvextsw2d VRT,VRB4@0|VRT@6|26@11|VRB@16|1538@21|v3.0
362Vector Extract Unsigned Byte to GPR using GPR-specified Left-Index VX-formvextublx RT,RA,VRB4@0|RT@6|RA@11|VRB@16|1549@21|v3.0
363Vector Extract Unsigned Byte to GPR using GPR-specified Right-Index VX-formvextubrx RT,RA,VRB4@0|RT@6|RA@11|VRB@16|1805@21|v3.0
364Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index VX-formvextuhlx RT,RA,VRB4@0|RT@6|RA@11|VRB@16|1613@21|v3.0
365Vector Extract Unsigned Halfword to GPR using GPR-specified Right-Index VX-formvextuhrx RT,RA,VRB4@0|RT@6|RA@11|VRB@16|1869@21|v3.0
366Vector Extract Unsigned Word to GPR using GPR-specified Left-Index VX-formvextuwlx RT,RA,VRB4@0|RT@6|RA@11|VRB@16|1677@21|v3.0
367Vector Extract Unsigned Word to GPR using GPR-specified Right-Index VX-formvextuwrx RT,RA,VRB4@0|RT@6|RA@11|VRB@16|1933@21|v3.0
368Vector Insert Byte from VSR using immediate-specified index VX-formvinsertb VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|781@21|v3.0
369Vector Insert Doubleword from VSR using immediate-specified index VX-formvinsertd VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|973@21|v3.0
370Vector Insert Halfword from VSR using immediate-specified index VX-formvinserth VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|845@21|v3.0
371Vector Insert Word from VSR using immediate-specified index VX-formvinsertw VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|909@21|v3.0
372Vector Multiply-by-10 & write Carry-out Unsigned Quadword VX-formvmul10cuq VRT,VRA4@0|VRT@6|VRA@11|///@16|1@21|v3.0
373Vector Multiply-by-10 Extended & write Carry-out Unsigned Quadword VX-formvmul10ecuq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|65@21|v3.0
374Vector Multiply-by-10 Extended Unsigned Quadword VX-formvmul10euq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|577@21|v3.0
375Vector Multiply-by-10 Unsigned Quadword VX-formvmul10uq VRT,VRA4@0|VRT@6|VRA@11|///@16|513@21|v3.0
376Vector Negate Doubleword VX-formvnegd VRT,VRB4@0|VRT@6|7@11|VRB@16|1538@21|v3.0
377Vector Negate Word VX-formvnegw VRT,VRB4@0|VRT@6|6@11|VRB@16|1538@21|v3.0
378Vector Permute Right-indexed VA-formvpermr VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|59@26|v3.0
379Vector Parity Byte Doubleword VX-formvprtybd VRT,VRB4@0|VRT@6|9@11|VRB@16|1538@21|v3.0
380Vector Parity Byte Quadword VX-formvprtybq VRT,VRB4@0|VRT@6|10@11|VRB@16|1538@21|v3.0
381Vector Parity Byte Word VX-formvprtybw VRT,VRB4@0|VRT@6|8@11|VRB@16|1538@21|v3.0
382Vector Rotate Left Doubleword then Mask Insert VX-formvrldmi VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|197@21|v3.0
383Vector Rotate Left Doubleword then AND with Mask VX-formvrldnm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|453@21|v3.0
384Vector Rotate Left Word then Mask Insert VX-formvrlwmi VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|133@21|v3.0
385Vector Rotate Left Word then AND with Mask VX-formvrlwnm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|389@21|v3.0
386Vector Shift Left Variable VX-formvslv VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1860@21|v3.0
387Vector Shift Right Variable VX-formvsrv VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1796@21|v3.0
388Wait X-formwait WC,PL31@0|??@6|/@8|WC@9|///@11|PL@14|///@16|30@21|/@31|v3.0
389VSX Scalar Absolute Quad-Precision X-formxsabsqp VRT,VRB63@0|VRT@6|0@11|VRB@16|804@21|/@31|v3.0
390VSX Scalar Add Quad-Precision [using round to Odd] X-formxsaddqp VRT,VRA,VRB (RO=0)|xsaddqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|4@21|RO@31|v3.0
391VSX Scalar Compare Equal Double-Precision XX3-formxscmpeqdp XT,XA,XB60@0|T@6|A@11|B@16|3@21|AX@29|BX@30|TX@31|v3.0
392VSX Scalar Compare Exponents Double-Precision XX3-formxscmpexpdp BF,XA,XB60@0|BF@6|//@9|A@11|B@16|59@21|AX@29|BX@30|/@31|v3.0
393VSX Scalar Compare Exponents Quad-Precision X-formxscmpexpqp BF,VRA,VRB63@0|BF@6|//@9|VRA@11|VRB@16|164@21|/@31|v3.0
394VSX Scalar Compare Greater Than or Equal Double-Precision XX3-formxscmpgedp XT,XA,XB60@0|T@6|A@11|B@16|19@21|AX@29|BX@30|TX@31|v3.0
395VSX Scalar Compare Greater Than Double-Precision XX3-formxscmpgtdp XT,XA,XB60@0|T@6|A@11|B@16|11@21|AX@29|BX@30|TX@31|v3.0
396VSX Scalar Compare Ordered Quad-Precision X-formxscmpoqp BF,VRA,VRB63@0|BF@6|//@9|VRA@11|VRB@16|132@21|/@31|v3.0
397VSX Scalar Compare Unordered Quad-Precision X-formxscmpuqp BF,VRA,VRB63@0|BF@6|//@9|VRA@11|VRB@16|644@21|/@31|v3.0
398VSX Scalar Copy Sign Quad-Precision X-formxscpsgnqp VRT,VRA,VRB63@0|VRT@6|VRA@11|VRB@16|100@21|/@31|v3.0
399VSX Scalar Convert with round Double-Precision to Half-Precision format XX2-formxscvdphp XT,XB60@0|T@6|17@11|B@16|347@21|BX@30|TX@31|v3.0
400VSX Scalar Convert Double-Precision to Quad-Precision format X-formxscvdpqp VRT,VRB63@0|VRT@6|22@11|VRB@16|836@21|/@31|v3.0
401VSX Scalar Convert Half-Precision to Double-Precision format XX2-formxscvhpdp XT,XB60@0|T@6|16@11|B@16|347@21|BX@30|TX@31|v3.0
402VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-formxscvqpdp VRT,VRB (RO=0)|xscvqpdpo VRT,VRB (RO=1)63@0|VRT@6|20@11|VRB@16|836@21|RO@31|v3.0
403VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-formxscvqpsdz VRT,VRB63@0|VRT@6|25@11|VRB@16|836@21|/@31|v3.0
404VSX Scalar Convert with round to zero Quad-Precision to Signed Word format X-formxscvqpswz VRT,VRB63@0|VRT@6|9@11|VRB@16|836@21|/@31|v3.0
405VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-formxscvqpudz VRT,VRB63@0|VRT@6|17@11|VRB@16|836@21|/@31|v3.0
406VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format X-formxscvqpuwz VRT,VRB63@0|VRT@6|1@11|VRB@16|836@21|/@31|v3.0
407VSX Scalar Convert Signed Doubleword to Quad-Precision format X-formxscvsdqp VRT,VRB63@0|VRT@6|10@11|VRB@16|836@21|/@31|v3.0
408VSX Scalar Convert Unsigned Doubleword to Quad-Precision format X-formxscvudqp VRT,VRB63@0|VRT@6|2@11|VRB@16|836@21|/@31|v3.0
409VSX Scalar Divide Quad-Precision [using round to Odd] X-formxsdivqp VRT,VRA,VRB (RO=0)|xsdivqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|548@21|RO@31|v3.0
410VSX Scalar Insert Exponent Double-Precision X-formxsiexpdp XT,RA,RB60@0|T@6|RA@11|RB@16|918@21|TX@31|v3.0
411VSX Scalar Insert Exponent Quad-Precision X-formxsiexpqp VRT,VRA,VRB63@0|VRT@6|VRA@11|VRB@16|868@21|/@31|v3.0
412VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-formxsmaddqp VRT,VRA,VRB (RO=0)|xsmaddqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|388@21|RO@31|v3.0
413VSX Scalar Maximum Type-C Double-Precision XX3-formxsmaxcdp XT,XA,XB60@0|T@6|A@11|B@16|128@21|AX@29|BX@30|TX@31|v3.0
414VSX Scalar Maximum Type-J Double-Precision XX3-formxsmaxjdp XT,XA,XB60@0|T@6|A@11|B@16|144@21|AX@29|BX@30|TX@31|v3.0
415VSX Scalar Minimum Type-C Double-Precision XX3-formxsmincdp XT,XA,XB60@0|T@6|A@11|B@16|136@21|AX@29|BX@30|TX@31|v3.0
416VSX Scalar Minimum Type-J Double-Precision XX3-formxsminjdp XT,XA,XB60@0|T@6|A@11|B@16|152@21|AX@29|BX@30|TX@31|v3.0
417VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-formxsmsubqp VRT,VRA,VRB (RO=0)|xsmsubqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|420@21|RO@31|v3.0
418VSX Scalar Multiply Quad-Precision [using round to Odd] X-formxsmulqp VRT,VRA,VRB (RO=0)|xsmulqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|36@21|RO@31|v3.0
419VSX Scalar Negative Absolute Quad-Precision X-formxsnabsqp VRT,VRB63@0|VRT@6|8@11|VRB@16|804@21|TX@31|v3.0
420VSX Scalar Negate Quad-Precision X-formxsnegqp VRT,VRB63@0|VRT@6|16@11|VRB@16|804@21|/@31|v3.0
421VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-formxsnmaddqp VRT,VRA,VRB (RO=0)|xsnmaddqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|452@21|RO@31|v3.0
422VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-formxsnmsubqp VRT,VRA,VRB (RO=0)|xsnmsubqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|484@21|RO@31|v3.0
423VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-formxsrqpi R,VRT,VRB,RMC (EX=0)|xsrqpix R,VRT,VRB,RMC (EX=1)63@0|VRT@6|///@11|R@15|VRB@16|RMC@21|5@23|EX@31|v3.0
424VSX Scalar Round Quad-Precision to Double-Extended Precision Z23-formxsrqpxp R,VRT,VRB,RMC63@0|VRT@6|///@11|R@15|VRB@16|RMC@21|37@23|/@31|v3.0
425VSX Scalar Square Root Quad-Precision [using round to Odd] X-formxssqrtqp VRT,VRB (RO=0)|xssqrtqpo VRT,VRB (RO=1)63@0|VRT@6|27@11|VRB@16|804@21|RO@31|v3.0
426VSX Scalar Subtract Quad-Precision [using round to Odd] X-formxssubqp VRT,VRA,VRB (RO=0)|xssubqpo VRT,VRA,VRB (RO=1)63@0|VRT@6|VRA@11|VRB@16|516@21|RO@31|v3.0
427VSX Scalar Test Data Class Double-Precision XX2-formxststdcdp BF,XB,DCMX60@0|BF@6|DCMX@9|B@16|362@21|BX@30|/@31|v3.0
428VSX Scalar Test Data Class Quad-Precision X-formxststdcqp BF,VRB,DCMX63@0|BF@6|DCMX@9|VRB@16|708@21|/@31|v3.0
429VSX Scalar Test Data Class Single-Precision XX2-formxststdcsp BF,XB,DCMX60@0|BF@6|DCMX@9|B@16|298@21|BX@30|/@31|v3.0
430VSX Scalar Extract Exponent Double-Precision XX2-formxsxexpdp RT,XB60@0|RT@6|0@11|B@16|347@21|BX@30|/@31|v3.0
431VSX Scalar Extract Exponent Quad-Precision X-formxsxexpqp VRT,VRB63@0|VRT@6|2@11|VRB@16|804@21|/@31|v3.0
432VSX Scalar Extract Significand Double-Precision XX2-formxsxsigdp RT,XB60@0|RT@6|1@11|B@16|347@21|BX@30|/@31|v3.0
433VSX Scalar Extract Significand Quad-Precision X-formxsxsigqp VRT,VRB63@0|VRT@6|18@11|VRB@16|804@21|/@31|v3.0
434VSX Vector Convert Half-Precision to Single-Precision format XX2-formxvcvhpsp XT,XB60@0|T@6|24@11|B@16|475@21|BX@30|TX@31|v3.0
435VSX Vector Convert with round Single-Precision to Half-Precision format XX2-formxvcvsphp XT,XB60@0|T@6|25@11|B@16|475@21|BX@30|TX@31|v3.0
436VSX Vector Insert Exponent Double-Precision XX3-formxviexpdp XT,XA,XB60@0|T@6|A@11|B@16|248@21|AX@29|BX@30|TX@31|v3.0
437VSX Vector Insert Exponent Single-Precision XX3-formxviexpsp XT,XA,XB60@0|T@6|A@11|B@16|216@21|AX@29|BX@30|TX@31|v3.0
438VSX Vector Test Data Class Double-Precision XX2-formxvtstdcdp XT,XB,DCMX60@0|T@6|dx@11|B@16|15@21|dc@25|5@26|dm@29|BX@30|TX@31|v3.0
439VSX Vector Test Data Class Single-Precision XX2-formxvtstdcsp XT,XB,DCMX60@0|T@6|dx@11|B@16|13@21|dc@25|5@26|dm@29|BX@30|TX@31|v3.0
440VSX Vector Extract Exponent Double-Precision XX2-formxvxexpdp XT,XB60@0|T@6|0@11|B@16|475@21|BX@30|TX@31|v3.0
441VSX Vector Extract Exponent Single-Precision XX2-formxvxexpsp XT,XB60@0|T@6|8@11|B@16|475@21|BX@30|TX@31|v3.0
442VSX Vector Extract Significand Double-Precision XX2-formxvxsigdp XT,XB60@0|T@6|1@11|B@16|475@21|BX@30|TX@31|v3.0
443VSX Vector Extract Significand Single-Precision XX2-formxvxsigsp XT,XB60@0|T@6|9@11|B@16|475@21|BX@30|TX@31|v3.0
444VSX Vector Byte-Reverse Doubleword XX2-formxxbrd XT,XB60@0|T@6|23@11|B@16|475@21|BX@30|TX@31|v3.0
445VSX Vector Byte-Reverse Halfword XX2-formxxbrh XT,XB60@0|T@6|7@11|B@16|475@21|BX@30|TX@31|v3.0
446VSX Vector Byte-Reverse Quadword XX2-formxxbrq XT,XB60@0|T@6|31@11|B@16|475@21|BX@30|TX@31|v3.0
447VSX Vector Byte-Reverse Word XX2-formxxbrw XT,XB60@0|T@6|15@11|B@16|475@21|BX@30|TX@31|v3.0
448VSX Vector Extract Unsigned Word XX2-formxxextractuw XT,XB,UIM60@0|T@6|/@11|UIM@12|B@16|165@21|BX@30|TX@31|v3.0
449VSX Vector Insert Word XX2-formxxinsertw XT,XB,UIM60@0|T@6|/@11|UIM@12|B@16|181@21|BX@30|TX@31|v3.0
450VSX Vector Permute XX3-formxxperm XT,XA,XB60@0|T@6|A@11|B@16|26@21|AX@29|BX@30|TX@31|v3.0
451VSX Vector Permute Right-indexed XX3-formxxpermr XT,XA,XB60@0|T@6|A@11|B@16|58@21|AX@29|BX@30|TX@31|v3.0
452VSX Vector Splat Immediate Byte X-formxxspltib XT,IMM860@0|T@6|0@11|IMM8@13|360@21|TX@31|v3.0
453Decimal Add Modulo VX-formbcdadd. VRT,VRA,VRB,PS4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|1@23|v2.07
454Decimal Subtract Modulo VX-formbcdsub. VRT,VRA,VRB,PS4@0|VRT@6|VRA@11|VRB@16|1@21|PS@22|65@23|v2.07
455Branch Conditional to Branch Target Address Register XL-formbctar BO,BI,BH (LK=0)|bctarl BO,BI,BH (LK=1)19@0|BO@6|BI@11|///@16|BH@19|560@21|LK@31|v2.07
456Clear BHRB X-formclrbhrb31@0|///@6|///@11|///@16|430@21|/@31|v2.07
457Floating Merge Even Word X-formfmrgew FRT,FRA,FRB63@0|FRT@6|FRA@11|FRB@16|966@21|/@31|v2.07
458Floating Merge Odd Word X-formfmrgow FRT,FRA,FRB63@0|FRT@6|FRA@11|FRB@16|838@21|/@31|v2.07
459Instruction Cache Block Touch X-formicbt CT, RA, RB31@0|/@6|CT@7|RA@11|RB@16|22@21|/@31|v2.07
460Load Quadword And Reserve Indexed X-formlqarx RTp,RA,RB,EH31@0|RTp@6|RA@11|RB@16|276@21|EH@31|v2.07
461Load VSX Scalar as Integer Word Algebraic Indexed X-formlxsiwax XT,RA,RB31@0|T@6|RA@11|RB@16|76@21|TX@31|v2.07
462Load VSX Scalar as Integer Word & Zero Indexed X-formlxsiwzx XT,RA,RB31@0|T@6|RA@11|RB@16|12@21|TX@31|v2.07
463Load VSX Scalar Single-Precision Indexed X-formlxsspx XT,RA,RB31@0|T@6|RA@11|RB@16|524@21|TX@31|v2.07
464Move From BHRB XFX-formmfbhrbe RT,BHRBE31@0|RT@6|BHRBE@11|302@21|/@31|v2.07
465Move From VSR Doubleword X-formmfvsrd RA,XS31@0|S@6|RA@11|///@16|51@21|SX@31|v2.07
466Move From VSR Word and Zero X-formmfvsrwz RA,XS31@0|S@6|RA@11|///@16|115@21|SX@31|v2.07
467Message Clear X-formmsgclr RB31@0|///@6|///@11|RB@16|238@21|/@31|v2.07
468Message Clear Privileged X-formmsgclrp RB31@0|///@6|///@11|RB@16|174@21|/@31|v2.07
469Message Send X-formmsgsnd RB31@0|///@6|///@11|RB@16|206@21|/@31|v2.07
470Message Send Privileged X-formmsgsndp RB31@0|///@6|///@11|RB@16|142@21|/@31|v2.07
471Move To VSR Doubleword X-formmtvsrd XT,RA31@0|T@6|RA@11|///@16|179@21|TX@31|v2.07
472Move To VSR Word Algebraic X-formmtvsrwa XT,RA31@0|T@6|RA@11|///@16|211@21|TX@31|v2.07
473Move To VSR Word and Zero X-formmtvsrwz XT,RA31@0|T@6|RA@11|///@16|243@21|TX@31|v2.07
474Return from Event Based Branch XL-formrfebb S19@0|///@6|///@11|///@16|S@20|146@21|/@31|v2.07
475Store Quadword Conditional Indexed X-formstqcx. RSp,RA,RB31@0|RSp@6|RA@11|RB@16|182@21|1@31|v2.07
476Store VSX Scalar as Integer Word Indexed X-formstxsiwx XS,RA,RB31@0|S@6|RA@11|RB@16|140@21|SX@31|v2.07
477Store VSX Scalar Single-Precision Indexed X-formstxsspx XS,RA,RB31@0|S@6|RA@11|RB@16|652@21|SX@31|v2.07
478Vector Add & write Carry Unsigned Quadword VX-formvaddcuq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|320@21|v2.07
479Vector Add Extended & write Carry Unsigned Quadword VA-formvaddecuq VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|61@26|v2.07
480Vector Add Extended Unsigned Quadword Modulo VA-formvaddeuqm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|60@26|v2.07
481Vector Add Unsigned Doubleword Modulo VX-formvaddudm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|192@21|v2.07
482Vector Add Unsigned Quadword Modulo VX-formvadduqm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|256@21|v2.07
483Vector Bit Permute Quadword VX-formvbpermq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1356@21|v2.07
484Vector AES Cipher VX-formvcipher VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1288@21|v2.07
485Vector AES Cipher Last VX-formvcipherlast VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1289@21|v2.07
486Vector Count Leading Zeros Byte VX-formvclzb VRT,VRB4@0|VRT@6|///@11|VRB@16|1794@21|v2.07
487Vector Count Leading Zeros Doubleword VX-formvclzd VRT,VRB4@0|VRT@6|///@11|VRB@16|1986@21|v2.07
488Vector Count Leading Zeros Halfword VX-formvclzh VRT,VRB4@0|VRT@6|///@11|VRB@16|1858@21|v2.07
489Vector Count Leading Zeros Word VX-formvclzw VRT,VRB4@0|VRT@6|///@11|VRB@16|1922@21|v2.07
490Vector Compare Equal Unsigned Doubleword VC-formvcmpequd VRT,VRA,VRB (Rc=0)|vcmpequd. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|199@22|v2.07
491Vector Compare Greater Than Signed Doubleword VC-formvcmpgtsd VRT,VRA,VRB (Rc=0)|vcmpgtsd. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|967@22|v2.07
492Vector Compare Greater Than Unsigned Doubleword VC-formvcmpgtud VRT,VRA,VRB (Rc=0)|vcmpgtud. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|711@22|v2.07
493Vector Logical Equivalence VX-formveqv VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1668@21|v2.07
494Vector Gather Bits by Bytes by Doubleword VX-formvgbbd VRT,VRB4@0|VRT@6|///@11|VRB@16|1292@21|v2.07
495Vector Maximum Signed Doubleword VX-formvmaxsd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|450@21|v2.07
496Vector Maximum Unsigned Doubleword VX-formvmaxud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|194@21|v2.07
497Vector Minimum Signed Doubleword VX-formvminsd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|962@21|v2.07
498Vector Minimum Unsigned Doubleword VX-formvminud VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|706@21|v2.07
499Vector Merge Even Word VX-formvmrgew VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1932@21|v2.07
500Vector Merge Odd Word VX-formvmrgow VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1676@21|v2.07
501Vector Multiply Even Signed Word VX-formvmulesw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|904@21|v2.07
502Vector Multiply Even Unsigned Word VX-formvmuleuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|648@21|v2.07
503Vector Multiply Odd Signed Word VX-formvmulosw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|392@21|v2.07
504Vector Multiply Odd Unsigned Word VX-formvmulouw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|136@21|v2.07
505Vector Multiply Unsigned Word Modulo VX-formvmuluwm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|137@21|v2.07
506Vector Logical NAND VX-formvnand VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1412@21|v2.07
507Vector AES Inverse Cipher VX-formvncipher VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1352@21|v2.07
508Vector AES Inverse Cipher Last VX-formvncipherlast VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1353@21|v2.07
509Vector Logical OR with Complement VX-formvorc VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1348@21|v2.07
510Vector Permute & Exclusive-OR VA-formvpermxor VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|45@26|v2.07
511Vector Pack Signed Doubleword Signed Saturate VX-formvpksdss VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1486@21|v2.07
512Vector Pack Signed Doubleword Unsigned Saturate VX-formvpksdus VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1358@21|v2.07
513Vector Pack Unsigned Doubleword Unsigned Modulo VX-formvpkudum VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1102@21|v2.07
514Vector Pack Unsigned Doubleword Unsigned Saturate VX-formvpkudus VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1230@21|v2.07
515Vector Polynomial Multiply-Sum Byte VX-formvpmsumb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1032@21|v2.07
516Vector Polynomial Multiply-Sum Doubleword VX-formvpmsumd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1224@21|v2.07
517Vector Polynomial Multiply-Sum Halfword VX-formvpmsumh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1096@21|v2.07
518Vector Polynomial Multiply-Sum Word VX-formvpmsumw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1160@21|v2.07
519Vector Population Count Byte VX-formvpopcntb VRT,VRB4@0|VRT@6|///@11|VRB@16|1795@21|v2.07
520Vector Population Count Doubleword VX-formvpopcntd VRT,VRB4@0|VRT@6|///@11|VRB@16|1987@21|v2.07
521Vector Population Count Halfword VX-formvpopcnth VRT,VRB4@0|VRT@6|///@11|VRB@16|1859@21|v2.07
522Vector Population Count Word VX-formvpopcntw VRT,VRB4@0|VRT@6|///@11|VRB@16|1923@21|v2.07
523Vector Rotate Left Doubleword VX-formvrld VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|196@21|v2.07
524Vector AES SubBytes VX-formvsbox VRT,VRA4@0|VRT@6|VRA@11|///@16|1480@21|v2.07
525Vector SHA-512 Sigma Doubleword VX-formvshasigmad VRT,VRA,ST,SIX4@0|VRT@6|VRA@11|ST@16|SIX@17|1730@21|v2.07
526Vector SHA-256 Sigma Word VX-formvshasigmaw VRT,VRA,ST,SIX4@0|VRT@6|VRA@11|ST@16|SIX@17|1666@21|v2.07
527Vector Shift Left Doubleword VX-formvsld VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1476@21|v2.07
528Vector Shift Right Algebraic Doubleword VX-formvsrad VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|964@21|v2.07
529Vector Shift Right Doubleword VX-formvsrd VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1732@21|v2.07
530Vector Subtract & write Carry-out Unsigned Quadword VX-formvsubcuq VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1344@21|v2.07
531Vector Subtract Extended & write Carry-out Unsigned Quadword VA-formvsubecuq VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|63@26|v2.07
532Vector Subtract Extended Unsigned Quadword Modulo VA-formvsubeuqm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|62@26|v2.07
533Vector Subtract Unsigned Doubleword Modulo VX-formvsubudm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1216@21|v2.07
534Vector Subtract Unsigned Quadword Modulo VX-formvsubuqm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1280@21|v2.07
535Vector Unpack High Signed Word VX-formvupkhsw VRT,VRB4@0|VRT@6|///@11|VRB@16|1614@21|v2.07
536Vector Unpack Low Signed Word VX-formvupklsw VRT,VRB4@0|VRT@6|///@11|VRB@16|1742@21|v2.07
537VSX Scalar Add Single-Precision XX3-formxsaddsp XT,XA,XB60@0|T@6|A@11|B@16|0@21|AX@29|BX@30|TX@31|v2.07
538VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-formxscvdpspn XT,XB60@0|T@6|///@11|B@16|267@21|BX@30|TX@31|v2.07
539VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-formxscvspdpn XT,XB60@0|T@6|///@11|B@16|331@21|BX@30|TX@31|v2.07
540VSX Scalar Convert with round Signed Doubleword to Single-Precision format XX2-formxscvsxdsp XT,XB60@0|T@6|///@11|B@16|312@21|BX@30|TX@31|v2.07
541VSX Scalar Convert with round Unsigned Doubleword to Single-Precision XX2-formxscvuxdsp XT,XB60@0|T@6|///@11|B@16|296@21|BX@30|TX@31|v2.07
542VSX Scalar Divide Single-Precision XX3-formxsdivsp XT,XA,XB60@0|T@6|A@11|B@16|24@21|AX@29|BX@30|TX@31|v2.07
543VSX Scalar Multiply-Add Type-A Single-Precision XX3-formxsmaddasp XT,XA,XB60@0|T@6|A@11|B@16|1@21|AX@29|BX@30|TX@31|v2.07
544VSX Scalar Multiply-Add Type-M Single-Precision XX3-formxsmaddmsp XT,XA,XB60@0|T@6|A@11|B@16|9@21|AX@29|BX@30|TX@31|v2.07
545VSX Scalar Multiply-Subtract Type-A Single-Precision XX3-formxsmsubasp XT,XA,XB60@0|T@6|A@11|B@16|17@21|AX@29|BX@30|TX@31|v2.07
546VSX Scalar Multiply-Subtract Type-M Single-Precision XX3-formxsmsubmsp XT,XA,XB60@0|T@6|A@11|B@16|25@21|AX@29|BX@30|TX@31|v2.07
547VSX Scalar Multiply Single-Precision XX3-formxsmulsp XT,XA,XB60@0|T@6|A@11|B@16|16@21|AX@29|BX@30|TX@31|v2.07
548VSX Scalar Negative Multiply-Add Type-A Single-Precision XX3-formxsnmaddasp XT,XA,XB60@0|T@6|A@11|B@16|129@21|AX@29|BX@30|TX@31|v2.07
549VSX Scalar Negative Multiply-Add Type-M Single-Precision XX3-formxsnmaddmsp XT,XA,XB60@0|T@6|A@11|B@16|137@21|AX@29|BX@30|TX@31|v2.07
550VSX Scalar Negative Multiply-Subtract Type-A Single-Precision XX3-formxsnmsubasp XT,XA,XB60@0|T@6|A@11|B@16|145@21|AX@29|BX@30|TX@31|v2.07
551VSX Scalar Negative Multiply-Subtract Type-M Single-Precision XX3-formxsnmsubmsp XT,XA,XB60@0|T@6|A@11|B@16|153@21|AX@29|BX@30|TX@31|v2.07
552VSX Scalar Reciprocal Estimate Single-Precision XX2-formxsresp XT,XB60@0|T@6|///@11|B@16|26@21|BX@30|TX@31|v2.07
553VSX Scalar Round to Single-Precision XX2-formxsrsp XT,XB60@0|T@6|///@11|B@16|281@21|BX@30|TX@31|v2.07
554VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-formxsrsqrtesp XT,XB60@0|T@6|///@11|B@16|10@21|BX@30|TX@31|v2.07
555VSX Scalar Square Root Single-Precision XX2-formxssqrtsp XT,XB60@0|T@6|///@11|B@16|11@21|BX@30|TX@31|v2.07
556VSX Scalar Subtract Single-Precision XX3-formxssubsp XT,XA,XB60@0|T@6|A@11|B@16|8@21|AX@29|BX@30|TX@31|v2.07
557VSX Vector Logical Equivalence XX3-formxxleqv XT,XA,XB60@0|T@6|A@11|B@16|186@21|AX@29|BX@30|TX@31|v2.07
558VSX Vector Logical NAND XX3-formxxlnand XT,XA,XB60@0|T@6|A@11|B@16|178@21|AX@29|BX@30|TX@31|v2.07
559VSX Vector Logical OR with Complement XX3-formxxlorc XT,XA,XB60@0|T@6|A@11|B@16|170@21|AX@29|BX@30|TX@31|v2.07
560Add and Generate Sixes XO-formaddg6s RT,RA,RB31@0|RT@6|RA@11|RB@16|/@21|74@22|/@31|v2.06
561Bit Permute Doubleword X-formbpermd RA,RS,RB31@0|RS@6|RA@11|RB@16|252@21|/@31|v2.06
562Convert Binary Coded Decimal To Declets X-formcbcdtd RA, RS31@0|RS@6|RA@11|///@16|314@21|/@31|v2.06
563Convert Declets To Binary Coded Decimal X-formcdtbcd RA, RS31@0|RS@6|RA@11|///@16|282@21|/@31|v2.06
564DFP Convert From Fixed X-formdcffix FRT,FRB (Rc=0)|dcffix. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|802@21|Rc@31|v2.06
565Divide Doubleword Extended XO-formdivde RT,RA,RB (OE=0 Rc=0)|divde. RT,RA,RB (OE=0 Rc=1)|divdeo RT,RA,RB (OE=1 Rc=0)|divdeo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|425@22|Rc@31|v2.06
566Divide Doubleword Extended Unsigned XO-formdivdeu RT,RA,RB (OE=0 Rc=0)|divdeu. RT,RA,RB (OE=0 Rc=1)|divdeuo RT,RA,RB (OE=1 Rc=0)|divdeuo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|393@22|Rc@31|v2.06
567Divide Word Extended XO-formdivwe RT,RA,RB (OE=0 Rc=0)|divwe. RT,RA,RB (OE=0 Rc=1)|divweo RT,RA,RB (OE=1 Rc=0)|divweo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|427@22|Rc@31|v2.06
568Divide Word Extended Unsigned XO-formdivweu RT,RA,RB (OE=0 Rc=0)|divweu. RT,RA,RB (OE=0 Rc=1)|divweuo RT,RA,RB (OE=1 Rc=0)|divweuo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|395@22|Rc@31|v2.06
569Floating Convert with round Signed Doubleword to Single-Precision format X-formfcfids FRT,FRB (Rc=0)|fcfids. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|846@21|Rc@31|v2.06
570Floating Convert with round Unsigned Doubleword to Double-Precision format X-formfcfidu FRT,FRB (Rc=0)|fcfidu. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|974@21|Rc@31|v2.06
571Floating Convert with round Unsigned Doubleword to Single-Precision format X-formfcfidus FRT,FRB (Rc=0)|fcfidus. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|974@21|Rc@31|v2.06
572Floating Convert with round Double-Precision To Unsigned Doubleword format X-formfctidu FRT,FRB (Rc=0)|fctidu. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|942@21|Rc@31|v2.06
573Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-formfctiduz FRT,FRB (Rc=0)|fctiduz. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|943@21|Rc@31|v2.06
574Floating Convert with round Double-Precision To Unsigned Word format X-formfctiwu FRT,FRB (Rc=0)|fctiwu. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|142@21|Rc@31|v2.06
575Floating Convert with truncate Double-Precision To Unsigned Word format X-formfctiwuz FRT,FRB (Rc=0)|fctiwuz. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|143@21|Rc@31|v2.06
576Floating Test for software Divide X-formftdiv BF,FRA,FRB63@0|BF@6|//@9|FRA@11|FRB@16|128@21|/@31|v2.06
577Floating Test for software Square Root X-formftsqrt BF,FRB63@0|BF@6|//@9|///@11|FRB@16|160@21|/@31|v2.06
578Load Byte And Reserve Indexed X-formlbarx RT,RA,RB,EH31@0|RT@6|RA@11|RB@16|52@21|EH@31|v2.06
579Load Doubleword Byte-Reverse Indexed X-formldbrx RT,RA,RB31@0|RT@6|RA@11|RB@16|532@21|/@31|v2.06
580Load Floating-Point as Integer Word & Zero Indexed X-formlfiwzx FRT,RA,RB31@0|FRT@6|RA@11|RB@16|887@21|/@31|v2.06
581Load Halfword And Reserve Indexed Xformlharx RT,RA,RB,EH31@0|RT@6|RA@11|RB@16|116@21|EH@31|v2.06
582Load VSX Scalar Doubleword Indexed X-formlxsdx XT,RA,RB31@0|T@6|RA@11|RB@16|588@21|TX@31|v2.06
583Load VSX Vector Doubleword*2 Indexed X-formlxvd2x XT,RA,RB31@0|T@6|RA@11|RB@16|844@21|TX@31|v2.06
584Load VSX Vector Doubleword & Splat Indexed X-formlxvdsx XT,RA,RB31@0|T@6|RA@11|RB@16|332@21|TX@31|v2.06
585Load VSX Vector Word*4 Indexed X-formlxvw4x XT,RA,RB31@0|T@6|RA@11|RB@16|780@21|TX@31|v2.06
586Population Count Doubleword X-formpopcntd RA, RS31@0|RS@6|RA@11|///@16|506@21|/@31|v2.06
587Population Count Words X-formpopcntw RA, RS31@0|RS@6|RA@11|///@16|378@21|/@31|v2.06
588Store Byte Conditional Indexed X-formstbcx. RS,RA,RB31@0|RS@6|RA@11|RB@16|694@21|1@31|v2.06
589Store Doubleword Byte-Reverse Indexed X-formstdbrx RS,RA,RB31@0|RS@6|RA@11|RB@16|660@21|/@31|v2.06
590Store Halfword Conditional Indexed X-formsthcx. RS,RA,RB31@0|RS@6|RA@11|RB@16|726@21|1@31|v2.06
591Store VSX Scalar Doubleword Indexed X-formstxsdx XS,RA,RB31@0|S@6|RA@11|RB@16|716@21|SX@31|v2.06
592Store VSX Vector Doubleword*2 Indexed X-formstxvd2x XS,RA,RB31@0|S@6|RA@11|RB@16|972@21|SX@31|v2.06
593Store VSX Vector Word*4 Indexed X-formstxvw4x XS,RA,RB31@0|S@6|RA@11|RB@16|908@21|SX@31|v2.06
594VSX Scalar Absolute Double-Precision XX2-formxsabsdp XT,XB60@0|T@6|///@11|B@16|345@21|BX@30|TX@31|v2.06
595VSX Scalar Add Double-Precision XX3-formxsadddp XT,XA,XB60@0|T@6|A@11|B@16|32@21|AX@29|BX@30|TX@31|v2.06
596VSX Scalar Compare Ordered Double-Precision XX3-formxscmpodp BF,XA,XB60@0|BF@6|//@9|A@11|B@16|43@21|AX@29|BX@30|/@31|v2.06
597VSX Scalar Compare Unordered Double-Precision XX3-formxscmpudp BF,XA,XB60@0|BF@6|//@9|A@11|B@16|35@21|AX@29|BX@30|/@31|v2.06
598VSX Scalar Copy Sign Double-Precision XX3-formxscpsgndp XT,XA,XB60@0|T@6|A@11|B@16|176@21|AX@29|BX@30|TX@31|v2.06
599VSX Scalar Convert with round Double-Precision to Single-Precision format XX2-formxscvdpsp XT,XB60@0|T@6|///@11|B@16|265@21|BX@30|TX@31|v2.06
600VSX Scalar Convert with round to zero Double-Precision to Signed Doubleword format XX2-formxscvdpsxds XT,XB60@0|T@6|///@11|B@16|344@21|BX@30|TX@31|v2.06
601VSX Scalar Convert with round to zero Double-Precision to Signed Word format XX2-formxscvdpsxws XT,XB60@0|T@6|///@11|B@16|88@21|BX@30|TX@31|v2.06
602VSX Scalar Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-formxscvdpuxds XT,XB60@0|T@6|///@11|B@16|328@21|BX@30|TX@31|v2.06
603VSX Scalar Convert with round to zero Double-Precision to Unsigned Word format XX2-formxscvdpuxws XT,XB60@0|T@6|///@11|B@16|72@21|BX@30|TX@31|v2.06
604VSX Scalar Convert Single-Precision to Double-Precision format XX2-formxscvspdp XT,XB60@0|T@6|///@11|B@16|329@21|BX@30|TX@31|v2.06
605VSX Scalar Convert with round Signed Doubleword to Double-Precision format XX2-formxscvsxddp XT,XB60@0|T@6|///@11|B@16|376@21|BX@30|TX@31|v2.06
606VSX Scalar Convert with round Unsigned Doubleword to Double-Precision format XX2-formxscvuxddp XT,XB60@0|T@6|///@11|B@16|360@21|BX@30|TX@31|v2.06
607VSX Scalar Divide Double-Precision XX3-formxsdivdp XT,XA,XB60@0|T@6|A@11|B@16|56@21|AX@29|BX@30|TX@31|v2.06
608VSX Scalar Multiply-Add Type-A Double-Precision XX3-formxsmaddadp XT,XA,XB60@0|T@6|A@11|B@16|33@21|AX@29|BX@30|TX@31|v2.06
609VSX Scalar Multiply-Add Type-M Double-Precision XX3-formxsmaddmdp XT,XA,XB60@0|T@6|A@11|B@16|41@21|AX@29|BX@30|TX@31|v2.06
610VSX Scalar Maximum Double-Precision XX3-formxsmaxdp XT,XA,XB60@0|T@6|A@11|B@16|160@21|AX@29|BX@30|TX@31|v2.06
611VSX Scalar Minimum Double-Precision XX3-formxsmindp XT,XA,XB60@0|T@6|A@11|B@16|168@21|AX@29|BX@30|TX@31|v2.06
612VSX Scalar Multiply-Subtract Type-A Double-Precision XX3-formxsmsubadp XT,XA,XB60@0|T@6|A@11|B@16|49@21|AX@29|BX@30|TX@31|v2.06
613VSX Scalar Multiply-Subtract Type-M Double-Precision XX3-formxsmsubmdp XT,XA,XB60@0|T@6|A@11|B@16|57@21|AX@29|BX@30|TX@31|v2.06
614VSX Scalar Multiply Double-Precision XX3-formxsmuldp XT,XA,XB60@0|T@6|A@11|B@16|48@21|AX@29|BX@30|TX@31|v2.06
615VSX Scalar Negative Absolute Double-Precision XX2-formxsnabsdp XT,XB60@0|T@6|///@11|B@16|361@21|BX@30|TX@31|v2.06
616VSX Scalar Negate Double-Precision XX2-formxsnegdp XT,XB60@0|T@6|///@11|B@16|377@21|BX@30|TX@31|v2.06
617VSX Scalar Negative Multiply-Add Type-A Double-Precision XX3-formxsnmaddadp XT,XA,XB60@0|T@6|A@11|B@16|161@21|AX@29|BX@30|TX@31|v2.06
618VSX Scalar Negative Multiply-Add Type-M Double-Precision XX3-formxsnmaddmdp XT,XA,XB60@0|T@6|A@11|B@16|169@21|AX@29|BX@30|TX@31|v2.06
619VSX Scalar Negative Multiply-Subtract Type-A Double-Precision XX3-formxsnmsubadp XT,XA,XB60@0|T@6|A@11|B@16|177@21|AX@29|BX@30|TX@31|v2.06
620VSX Scalar Negative Multiply-Subtract Type-M Double-Precision XX3-formxsnmsubmdp XT,XA,XB60@0|T@6|A@11|B@16|185@21|AX@29|BX@30|TX@31|v2.06
621VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-formxsrdpi XT,XB60@0|T@6|///@11|B@16|73@21|BX@30|TX@31|v2.06
622VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-formxsrdpic XT,XB60@0|T@6|///@11|B@16|107@21|BX@30|TX@31|v2.06
623VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-formxsrdpim XT,XB60@0|T@6|///@11|B@16|121@21|BX@30|TX@31|v2.06
624VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-formxsrdpip XT,XB60@0|T@6|///@11|B@16|105@21|BX@30|TX@31|v2.06
625VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-formxsrdpiz XT,XB60@0|T@6|///@11|B@16|89@21|BX@30|TX@31|v2.06
626VSX Scalar Reciprocal Estimate Double-Precision XX2-formxsredp XT,XB60@0|T@6|///@11|B@16|90@21|BX@30|TX@31|v2.06
627VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-formxsrsqrtedp XT,XB60@0|T@6|///@11|B@16|74@21|BX@30|TX@31|v2.06
628VSX Scalar Square Root Double-Precision XX2-formxssqrtdp XT,XB60@0|T@6|///@11|B@16|75@21|BX@30|TX@31|v2.06
629VSX Scalar Subtract Double-Precision XX3-formxssubdp XT,XA,XB60@0|T@6|A@11|B@16|40@21|AX@29|BX@30|TX@31|v2.06
630VSX Scalar Test for software Divide Double-Precision XX3-formxstdivdp BF,XA,XB60@0|BF@6|//@9|A@11|B@16|61@21|AX@29|BX@30|/@31|v2.06
631VSX Scalar Test for software Square Root Double-Precision XX2-formxstsqrtdp BF,XB60@0|BF@6|//@9|///@11|B@16|106@21|BX@30|/@31|v2.06
632VSX Vector Absolute Value Double-Precision XX2-formxvabsdp XT,XB60@0|T@6|///@11|B@16|473@21|BX@30|TX@31|v2.06
633VSX Vector Absolute Value Single-Precision XX2-formxvabssp XT,XB60@0|T@6|///@11|B@16|409@21|BX@30|TX@31|v2.06
634VSX Vector Add Double-Precision XX3-formxvadddp XT,XA,XB60@0|T@6|A@11|B@16|96@21|AX@29|BX@30|TX@31|v2.06
635VSX Vector Add Single-Precision XX3-formxvaddsp XT,XA,XB60@0|T@6|A@11|B@16|64@21|AX@29|BX@30|TX@31|v2.06
636VSX Vector Compare Equal To Double-Precision XX3-formxvcmpeqdp XT,XA,XB (Rc=0)|xvcmpeqdp. XT,XA,XB (Rc=1)60@0|T@6|A@11|B@16|Rc@21|99@22|AX@29|BX@30|TX@31|v2.06
637VSX Vector Compare Equal To Single-Precision XX3-formxvcmpeqsp XT,XA,XB (Rc=0)|xvcmpeqsp. XT,XA,XB (Rc=1)60@0|T@6|A@11|B@16|Rc@21|67@22|AX@29|BX@30|TX@31|v2.06
638VSX Vector Compare Greater Than or Equal To Double-Precision XX3-formxvcmpgedp XT,XA,XB (Rc=0)|xvcmpgedp. XT,XA,XB (Rc=1)60@0|T@6|A@11|B@16|Rc@21|115@22|AX@29|BX@30|TX@31|v2.06
639VSX Vector Compare Greater Than or Equal To Single-Precision XX3-formxvcmpgesp XT,XA,XB (Rc=0)|xvcmpgesp. XT,XA,XB (Rc=1)60@0|T@6|A@11|B@16|Rc@21|83@22|AX@29|BX@30|TX@31|v2.06
640VSX Vector Compare Greater Than Double-Precision XX3-formxvcmpgtdp XT,XA,XB (Rc=0)|xvcmpgtdp. XT,XA,XB (Rc=1)60@0|T@6|A@11|B@16|Rc@21|107@22|AX@29|BX@30|TX@31|v2.06
641VSX Vector Compare Greater Than Single-Precision XX3-formxvcmpgtsp XT,XA,XB (Rc=0)|xvcmpgtsp. XT,XA,XB (Rc=1)60@0|T@6|A@11|B@16|Rc@21|75@22|AX@29|BX@30|TX@31|v2.06
642VSX Vector Copy Sign Double-Precision XX3-formxvcpsgndp XT,XA,XB60@0|T@6|A@11|B@16|240@21|AX@29|BX@30|TX@31|v2.06
643VSX Vector Copy Sign Single-Precision XX3-formxvcpsgnsp XT,XA,XB60@0|T@6|A@11|B@16|208@21|AX@29|BX@30|TX@31|v2.06
644VSX Vector Convert with round Double-Precision to Single-Precision format XX2-formxvcvdpsp XT,XB60@0|T@6|///@11|B@16|393@21|BX@30|TX@31|v2.06
645VSX Vector Convert with round to zero Double-Precision to Signed Doubleword format XX2-formxvcvdpsxds XT,XB60@0|T@6|///@11|B@16|472@21|BX@30|TX@31|v2.06
646VSX Vector Convert with round to zero Double-Precision to Signed Word format XX2-formxvcvdpsxws XT,XB60@0|T@6|///@11|B@16|216@21|BX@30|TX@31|v2.06
647VSX Vector Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-formxvcvdpuxds XT,XB60@0|T@6|///@11|B@16|456@21|BX@30|TX@31|v2.06
648VSX Vector Convert with round to zero Double-Precision to Unsigned Word format XX2-formxvcvdpuxws XT,XB60@0|T@6|///@11|B@16|200@21|BX@30|TX@31|v2.06
649VSX Vector Convert Single-Precision to Double-Precision format XX2-formxvcvspdp XT,XB60@0|T@6|///@11|B@16|457@21|BX@30|TX@31|v2.06
650VSX Vector Convert with round to zero Single-Precision to Signed Doubleword format XX2-formxvcvspsxds XT,XB60@0|T@6|///@11|B@16|408@21|BX@30|TX@31|v2.06
651VSX Vector Convert with round to zero Single-Precision to Signed Word format XX2-formxvcvspsxws XT,XB60@0|T@6|///@11|B@16|152@21|BX@30|TX@31|v2.06
652VSX Vector Convert with round to zero Single-Precision to Unsigned Doubleword format XX2-formxvcvspuxds XT,XB60@0|T@6|///@11|B@16|392@21|BX@30|TX@31|v2.06
653VSX Vector Convert with round to zero Single-Precision to Unsigned Word format XX2-formxvcvspuxws XT,XB60@0|T@6|///@11|B@16|136@21|BX@30|TX@31|v2.06
654VSX Vector Convert with round Signed Doubleword to Double-Precision format XX2-formxvcvsxddp XT,XB60@0|T@6|///@11|B@16|504@21|BX@30|TX@31|v2.06
655VSX Vector Convert with round Signed Doubleword to Single-Precision format XX2-formxvcvsxdsp XT,XB60@0|T@6|///@11|B@16|440@21|BX@30|TX@31|v2.06
656VSX Vector Convert Signed Word to Double-Precision format XX2-formxvcvsxwdp XT,XB60@0|T@6|///@11|B@16|248@21|BX@30|TX@31|v2.06
657VSX Vector Convert with round Signed Word to Single-Precision format XX2-formxvcvsxwsp XT,XB60@0|T@6|///@11|B@16|184@21|BX@30|TX@31|v2.06
658VSX Vector Convert with round Unsigned Doubleword to Double-Precision format XX2-formxvcvuxddp XT,XB60@0|T@6|///@11|B@16|488@21|BX@30|TX@31|v2.06
659VSX Vector Convert with round Unsigned Doubleword to Single-Precision format XX2-formxvcvuxdsp XT,XB60@0|T@6|///@11|B@16|424@21|BX@30|TX@31|v2.06
660VSX Vector Convert Unsigned Word to Double-Precision format XX2-formxvcvuxwdp XT,XB60@0|T@6|///@11|B@16|232@21|BX@30|TX@31|v2.06
661VSX Vector Convert with round Unsigned Word to Single-Precision format XX2-formxvcvuxwsp XT,XB60@0|T@6|///@11|B@16|168@21|BX@30|TX@31|v2.06
662VSX Vector Divide Double-Precision XX3-formxvdivdp XT,XA,XB60@0|T@6|A@11|B@16|120@21|AX@29|BX@30|TX@31|v2.06
663VSX Vector Divide Single-Precision XX3-formxvdivsp XT,XA,XB60@0|T@6|A@11|B@16|88@21|AX@29|BX@30|TX@31|v2.06
664VSX Vector Multiply-Add Type-A Double-Precision XX3-formxvmaddadp XT,XA,XB60@0|T@6|A@11|B@16|97@21|AX@29|BX@30|TX@31|v2.06
665VSX Vector Multiply-Add Type-A Single-Precision XX3-formxvmaddasp XT,XA,XB60@0|T@6|A@11|B@16|65@21|AX@29|BX@30|TX@31|v2.06
666VSX Vector Multiply-Add Type-M Double-Precision XX3-formxvmaddmdp XT,XA,XB60@0|T@6|A@11|B@16|105@21|AX@29|BX@30|TX@31|v2.06
667VSX Vector Multiply-Add Type-M Single-Precision XX3-formxvmaddmsp XT,XA,XB60@0|T@6|A@11|B@16|73@21|AX@29|BX@30|TX@31|v2.06
668VSX Vector Maximum Double-Precision XX3-formxvmaxdp XT,XA,XB60@0|T@6|A@11|B@16|224@21|AX@29|BX@30|TX@31|v2.06
669VSX Vector Maximum Single-Precision XX3-formxvmaxsp XT,XA,XB60@0|T@6|A@11|B@16|192@21|AX@29|BX@30|TX@31|v2.06
670VSX Vector Minimum Double-Precision XX3-formxvmindp XT,XA,XB60@0|T@6|A@11|B@16|232@21|AX@29|BX@30|TX@31|v2.06
671VSX Vector Minimum Single-Precision XX3-formxvminsp XT,XA,XB60@0|T@6|A@11|B@16|200@21|AX@29|BX@30|TX@31|v2.06
672VSX Vector Multiply-Subtract Type-A Double-Precision XX3-formxvmsubadp XT,XA,XB60@0|T@6|A@11|B@16|113@21|AX@29|BX@30|TX@31|v2.06
673VSX Vector Multiply-Subtract Type-A Single-Precision XX3-formxvmsubasp XT,XA,XB60@0|T@6|A@11|B@16|81@21|AX@29|BX@30|TX@31|v2.06
674VSX Vector Multiply-Subtract Type-M Double-Precision XX3-formxvmsubmdp XT,XA,XB60@0|T@6|A@11|B@16|121@21|AX@29|BX@30|TX@31|v2.06
675VSX Vector Multiply-Subtract Type-M Single-Precision XX3-formxvmsubmsp XT,XA,XB60@0|T@6|A@11|B@16|89@21|AX@29|BX@30|TX@31|v2.06
676VSX Vector Multiply Double-Precision XX3-formxvmuldp XT,XA,XB60@0|T@6|A@11|B@16|112@21|AX@29|BX@30|TX@31|v2.06
677VSX Vector Multiply Single-Precision XX3-formxvmulsp XT,XA,XB60@0|T@6|A@11|B@16|80@21|AX@29|BX@30|TX@31|v2.06
678VSX Vector Negative Absolute Double-Precision XX2-formxvnabsdp XT,XB60@0|T@6|///@11|B@16|489@21|BX@30|TX@31|v2.06
679VSX Vector Negative Absolute Single-Precision XX2-formxvnabssp XT,XB60@0|T@6|///@11|B@16|425@21|BX@30|TX@31|v2.06
680VSX Vector Negate Double-Precision XX2-formxvnegdp XT,XB60@0|T@6|///@11|B@16|505@21|BX@30|TX@31|v2.06
681VSX Vector Negate Single-Precision XX2-formxvnegsp XT,XB60@0|T@6|///@11|B@16|441@21|BX@30|TX@31|v2.06
682VSX Vector Negative Multiply-Add Type-A Double-Precision XX3-formxvnmaddadp XT,XA,XB60@0|T@6|A@11|B@16|225@21|AX@29|BX@30|TX@31|v2.06
683VSX Vector Negative Multiply-Add Type-A Single-Precision XX3-formxvnmaddasp XT,XA,XB60@0|T@6|A@11|B@16|193@21|AX@29|BX@30|TX@31|v2.06
684VSX Vector Negative Multiply-Add Type-M Double-Precision XX3-formxvnmaddmdp XT,XA,XB60@0|T@6|A@11|B@16|233@21|AX@29|BX@30|TX@31|v2.06
685VSX Vector Negative Multiply-Add Type-M Single-Precision XX3-formxvnmaddmsp XT,XA,XB60@0|T@6|A@11|B@16|201@21|AX@29|BX@30|TX@31|v2.06
686VSX Vector Negative Multiply-Subtract Type-A Double-Precision XX3-formxvnmsubadp XT,XA,XB60@0|T@6|A@11|B@16|241@21|AX@29|BX@30|TX@31|v2.06
687VSX Vector Negative Multiply-Subtract Type-A Single-Precision XX3-formxvnmsubasp XT,XA,XB60@0|T@6|A@11|B@16|209@21|AX@29|BX@30|TX@31|v2.06
688VSX Vector Negative Multiply-Subtract Type-M Double-Precision XX3-formxvnmsubmdp XT,XA,XB60@0|T@6|A@11|B@16|249@21|AX@29|BX@30|TX@31|v2.06
689VSX Vector Negative Multiply-Subtract Type-M Single-Precision XX3-formxvnmsubmsp XT,XA,XB60@0|T@6|A@11|B@16|217@21|AX@29|BX@30|TX@31|v2.06
690VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-formxvrdpi XT,XB60@0|T@6|///@11|B@16|201@21|BX@30|TX@31|v2.06
691VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-formxvrdpic XT,XB60@0|T@6|///@11|B@16|235@21|BX@30|TX@31|v2.06
692VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-formxvrdpim XT,XB60@0|T@6|///@11|B@16|249@21|BX@30|TX@31|v2.06
693VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-formxvrdpip XT,XB60@0|T@6|///@11|B@16|233@21|BX@30|TX@31|v2.06
694VSX Vector Round to Double-Precision Integer using round toward Zero XX2-formxvrdpiz XT,XB60@0|T@6|///@11|B@16|217@21|BX@30|TX@31|v2.06
695VSX Vector Reciprocal Estimate Double-Precision XX2-formxvredp XT,XB60@0|T@6|///@11|B@16|218@21|BX@30|TX@31|v2.06
696VSX Vector Reciprocal Estimate Single-Precision XX2-formxvresp XT,XB60@0|T@6|///@11|B@16|154@21|BX@30|TX@31|v2.06
697VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-formxvrspi XT,XB60@0|T@6|///@11|B@16|137@21|BX@30|TX@31|v2.06
698VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-formxvrspic XT,XB60@0|T@6|///@11|B@16|171@21|BX@30|TX@31|v2.06
699VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-formxvrspim XT,XB60@0|T@6|///@11|B@16|185@21|BX@30|TX@31|v2.06
700VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-formxvrspip XT,XB60@0|T@6|///@11|B@16|169@21|BX@30|TX@31|v2.06
701VSX Vector Round to Single-Precision Integer using round toward Zero XX2-formxvrspiz XT,XB60@0|T@6|///@11|B@16|153@21|BX@30|TX@31|v2.06
702VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-formxvrsqrtedp XT,XB60@0|T@6|///@11|B@16|202@21|BX@30|TX@31|v2.06
703VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-formxvrsqrtesp XT,XB60@0|T@6|///@11|B@16|138@21|BX@30|TX@31|v2.06
704VSX Vector Square Root Double-Precision XX2-formxvsqrtdp XT,XB60@0|T@6|///@11|B@16|203@21|BX@30|TX@31|v2.06
705VSX Vector Square Root Single-Precision XX2-formxvsqrtsp XT,XB60@0|T@6|///@11|B@16|139@21|BX@30|TX@31|v2.06
706VSX Vector Subtract Double-Precision XX3-formxvsubdp XT,XA,XB60@0|T@6|A@11|B@16|104@21|AX@29|BX@30|TX@31|v2.06
707VSX Vector Subtract Single-Precision XX3-formxvsubsp XT,XA,XB60@0|T@6|A@11|B@16|72@21|AX@29|BX@30|TX@31|v2.06
708VSX Vector Test for software Divide Double-Precision XX3-formxvtdivdp BF,XA,XB60@0|BF@6|//@9|A@11|B@16|125@21|AX@29|BX@30|/@31|v2.06
709VSX Vector Test for software Divide Single-Precision XX3-formxvtdivsp BF,XA,XB60@0|BF@6|//@9|A@11|B@16|93@21|AX@29|BX@30|/@31|v2.06
710VSX Vector Test for software Square Root Double-Precision XX2-formxvtsqrtdp BF,XB60@0|BF@6|//@9|///@11|B@16|234@21|BX@30|/@31|v2.06
711VSX Vector Test for software Square Root Single-Precision XX2-formxvtsqrtsp BF,XB60@0|BF@6|//@9|///@11|B@16|170@21|BX@30|/@31|v2.06
712VSX Vector Logical AND XX3-formxxland XT,XA,XB60@0|T@6|A@11|B@16|130@21|AX@29|BX@30|TX@31|v2.06
713VSX Vector Logical AND with Complement XX3-formxxlandc XT,XA,XB60@0|T@6|A@11|B@16|138@21|AX@29|BX@30|TX@31|v2.06
714VSX Vector Logical NOR XX3-formxxlnor XT,XA,XB60@0|T@6|A@11|B@16|162@21|AX@29|BX@30|TX@31|v2.06
715VSX Vector Logical OR XX3-formxxlor XT,XA,XB60@0|T@6|A@11|B@16|146@21|AX@29|BX@30|TX@31|v2.06
716VSX Vector Logical XOR XX3-formxxlxor XT,XA,XB60@0|T@6|A@11|B@16|154@21|AX@29|BX@30|TX@31|v2.06
717VSX Vector Merge High Word XX3-formxxmrghw XT,XA,XB60@0|T@6|A@11|B@16|18@21|AX@29|BX@30|TX@31|v2.06
718VSX Vector Merge Low Word XX3-formxxmrglw XT,XA,XB60@0|T@6|A@11|B@16|50@21|AX@29|BX@30|TX@31|v2.06
719VSX Vector Permute Doubleword Immediate XX3-formxxpermdi XT,XA,XB,DM60@0|T@6|A@11|B@16|0@21|DM@22|10@24|AX@29|BX@30|TX@31|v2.06
720VSX Vector Select XX4-formxxsel XT,XA,XB,XC60@0|T@6|A@11|B@16|C@21|3@26|CX@28|AX@29|BX@30|TX@31|v2.06
721VSX Vector Shift Left Double by Word Immediate XX3-formxxsldwi XT,XA,XB,SHW60@0|T@6|A@11|B@16|0@21|SHW@22|2@24|AX@29|BX@30|TX@31|v2.06
722VSX Vector Splat Word XX2-formxxspltw XT,XB,UIM60@0|T@6|///@11|UIM@14|B@16|164@21|BX@30|TX@31|v2.06
723Compare Bytes X-formcmpb RA,RS,RB31@0|RS@6|RA@11|RB@16|508@21|/@31|v2.05
724DFP Add X-formdadd FRT,FRA,FRB (Rc=0)|dadd. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|2@21|Rc@31|v2.05
725DFP Add Quad X-formdaddq FRTp,FRAp,FRBp (Rc=0)|daddq. FRTp,FRAp,FRBp (Rc=1)63@0|FRTp@6|FRAp@11|FRBp@16|2@21|Rc@31|v2.05
726DFP Convert From Fixed Quad X-formdcffixq FRTp,FRB (Rc=0)|dcffixq. FRTp,FRB (Rc=1)63@0|FRTp@6|///@11|FRB@16|802@21|Rc@31|v2.05
727DFP Compare Ordered X-formdcmpo BF,FRA,FRB59@0|BF@6|//@9|FRA@11|FRB@16|130@21|/@31|v2.05
728DFP Compare Ordered Quad X-formdcmpoq BF,FRAp,FRBp63@0|BF@6|//@9|FRAp@11|FRBp@16|130@21|/@31|v2.05
729DFP Compare Unordered X-formdcmpu BF,FRA,FRB59@0|BF@6|//@9|FRA@11|FRB@16|642@21|/@31|v2.05
730DFP Compare Unordered Quad X-formdcmpuq BF,FRAp,FRBp63@0|BF@6|//@9|FRAp@11|FRBp@16|642@21|/@31|v2.05
731DFP Convert To DFP Long X-formdctdp FRT,FRB (Rc=0)|dctdp. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|258@21|Rc@31|v2.05
732DFP Convert To Fixed X-formdctfix FRT,FRB (Rc=0)|dctfix. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|290@21|Rc@31|v2.05
733DFP Convert To Fixed Quad X-formdctfixq FRT,FRBp (Rc=0)|dctfixq. FRT,FRBp (Rc=1)63@0|FRT@6|///@11|FRBp@16|290@21|Rc@31|v2.05
734DFP Convert To DFP Extended X-formdctqpq FRTp,FRB (Rc=0)|dctqpq. FRTp,FRB (Rc=1)63@0|FRTp@6|///@11|FRB@16|258@21|Rc@31|v2.05
735DFP Decode DPD To BCD X-formddedpd SP,FRT,FRB (Rc=0)|ddedpd. SP,FRT,FRB (Rc=1)59@0|FRT@6|SP@11|///@13|FRB@16|322@21|Rc@31|v2.05
736DFP Decode DPD To BCD Quad X-formddedpdq SP,FRTp,FRBp (Rc=0)|ddedpdq. SP,FRTp,FRBp (Rc=1)63@0|FRTp@6|SP@11|///@13|FRBp@16|322@21|Rc@31|v2.05
737DFP Divide X-formddiv FRT,FRA,FRB (Rc=0)|ddiv. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|546@21|Rc@31|v2.05
738DFP Divide Quad X-formddivq FRTp,FRAp,FRBp (Rc=0)|ddivq. FRTp,FRAp,FRBp (Rc=1)63@0|FRTp@6|FRAp@11|FRBp@16|546@21|Rc@31|v2.05
739DFP Encode BCD To DPD X-formdenbcd S,FRT,FRB (Rc=0)|denbcd. S,FRT,FRB (Rc=1)59@0|FRT@6|S@11|///@12|FRB@16|834@21|Rc@31|v2.05
740DFP Encode BCD To DPD Quad X-formdenbcdq S,FRTp,FRBp (Rc=0)|denbcdq. S,FRTp,FRBp (Rc=1)63@0|FRTp@6|S@11|///@12|FRBp@16|834@21|Rc@31|v2.05
741DFP Insert Biased Exponent X-formdiex FRT,FRA,FRB (Rc=0)|diex. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|866@21|Rc@31|v2.05
742DFP Insert Biased Exponent Quad X-formdiexq FRTp,FRA,FRBp|diexq. FRTp,FRA,FRBp (Rc=1)63@0|FRTp@6|FRA@11|FRBp@16|866@21|Rc@31|v2.05
743DFP Multiply X-formdmul FRT,FRA,FRB (Rc=0)|dmul. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|34@21|Rc@31|v2.05
744DFP Multiply Quad X-formdmulq FRTp,FRAp,FRBp (Rc=0)|dmulq. FRTp,FRAp,FRBp (Rc=1)63@0|FRTp@6|FRAp@11|FRBp@16|34@21|Rc@31|v2.05
745DFP Quantize Z23-formdqua FRT,FRA,FRB,RMC (Rc=0)|dqua. FRT,FRA,FRB,RMC (Rc=1)59@0|FRT@6|FRA@11|FRB@16|RMC@21|3@23|Rc@31|v2.05
746DFP Quantize Immediate Z23-formdquai TE,FRT,FRB,RMC (Rc=0)|dquai. TE,FRT,FRB,RMC (Rc=1)59@0|FRT@6|TE@11|FRB@16|RMC@21|67@23|Rc@31|v2.05
747DFP Quantize Immediate Quad Z23-formdquaiq TE,FRTp,FRBp,RMC (Rc=0)|dquaiq. TE,FRTp,FRBp,RMC (Rc=1)63@0|FRTp@6|TE@11|FRBp@16|RMC@21|67@23|Rc@31|v2.05
748DFP Quantize Quad Z23-formdquaq FRTp,FRAp,FRBp,RMC (Rc=0)|dquaq. FRTp,FRAp,FRBp,RMC (Rc=1)63@0|FRTp@6|FRAp@11|FRBp@16|RMC@21|3@23|Rc@31|v2.05
749DFP Round To DFP Long X-formdrdpq FRTp,FRBp (Rc=0)|drdpq. FRTp,FRBp (Rc=1)63@0|FRTp@6|///@11|FRBp@16|770@21|Rc@31|v2.05
750DFP Round To FP Integer Without Inexact Z23-formdrintn R,FRT,FRB,RMC (Rc=0)|drintn. R,FRT,FRB,RMC (Rc=1)59@0|FRT@6|///@11|R@15|FRB@16|RMC@21|227@23|Rc@31|v2.05
751DFP Round To FP Integer Without Inexact Quad Z23-formdrintnq R,FRTp,FRBp,RMC (Rc=0)|drintnq. R,FRTp,FRBp,RMC (Rc=1)63@0|FRTp@6|///@11|R@15|FRBp@16|RMC@21|227@23|Rc@31|v2.05
752DFP Round To FP Integer With Inexact Z23-formdrintx R,FRT,FRB,RMC (Rc=0)|drintx. R,FRT,FRB,RMC (Rc=1)59@0|FRT@6|///@11|R@15|FRB@16|RMC@21|99@23|Rc@31|v2.05
753DFP Round To FP Integer With Inexact Quad Z23-formdrintxq R,FRTp,FRBp,RMC (Rc=0)|drintxq. R,FRTp,FRBp,RMC (Rc=1)63@0|FRTp@6|///@11|R@15|FRBp@16|RMC@21|99@23|Rc@31|v2.05
754DFP Reround Z23-formdrrnd FRT,FRA,FRB,RMC (Rc=0)|drrnd. FRT,FRA,FRB,RMC (Rc=1)59@0|FRT@6|FRA@11|FRB@16|RMC@21|35@23|Rc@31|v2.05
755DFP Reround Quad Z23-formdrrndq FRTp,FRA,FRBp,RMC (Rc=0)|drrndq. FRTp,FRA,FRBp,RMC (Rc=1)63@0|FRTp@6|FRA@11|FRBp@16|RMC@21|35@23|Rc@31|v2.05
756DFP Round To DFP Short X-formdrsp FRT,FRB (Rc=0)|drsp. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|770@21|Rc@31|v2.05
757DFP Shift Significand Left Immediate Z22-formdscli FRT,FRA,SH (Rc=0)|dscli. FRT,FRA,SH (Rc=1)59@0|FRT@6|FRA@11|SH@16|66@22|Rc@31|v2.05
758DFP Shift Significand Left Immediate Quad Z22-formdscliq FRTp,FRAp,SH (Rc=0)|dscliq. FRTp,FRAp,SH (Rc=1)63@0|FRTp@6|FRAp@11|SH@16|66@22|Rc@31|v2.05
759DFP Shift Significand Right Immediate Z22-formdscri FRT,FRA,SH (Rc=0)|dscri. FRT,FRA,SH (Rc=1)59@0|FRT@6|FRA@11|SH@16|98@22|Rc@31|v2.05
760DFP Shift Significand Right Immediate Quad Z22-formdscriq FRTp,FRAp,SH (Rc=0)|dscriq. FRTp,FRAp,SH (Rc=1)63@0|FRTp@6|FRAp@11|SH@16|98@22|Rc@31|v2.05
761DFP Subtract X-formdsub FRT,FRA,FRB (Rc=0)|dsub. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|514@21|Rc@31|v2.05
762DFP Subtract Quad X-formdsubq FRTp,FRAp,FRBp (Rc=0)|dsubq. FRTp,FRAp,FRBp (Rc=1)63@0|FRTp@6|FRAp@11|FRBp@16|514@21|Rc@31|v2.05
763DFP Test Data Class Z22-formdtstdc BF,FRA,DCM59@0|BF@6|//@9|FRA@11|DCM@16|194@22|/@31|v2.05
764DFP Test Data Class Quad Z22-formdtstdcq BF,FRAp,DCM63@0|BF@6|//@9|FRAp@11|DCM@16|194@22|/@31|v2.05
765DFP Test Data Group Z22-formdtstdg BF,FRA,DGM59@0|BF@6|//@9|FRA@11|DGM@16|226@22|/@31|v2.05
766DFP Test Data Group Quad Z22-formdtstdgq BF,FRAp,DGM63@0|BF@6|//@9|FRAp@11|DGM@16|226@22|/@31|v2.05
767DFP Test Exponent X-formdtstex BF,FRA,FRB59@0|BF@6|//@9|FRA@11|FRB@16|162@21|/@31|v2.05
768DFP Test Exponent Quad X-formdtstexq BF,FRAp,FRBp63@0|BF@6|//@9|FRAp@11|FRBp@16|162@21|/@31|v2.05
769DFP Test Significance X-formdtstsf BF,FRA,FRB59@0|BF@6|//@9|FRA@11|FRB@16|674@21|/@31|v2.05
770DFP Test Significance Quad X-formdtstsfq BF,FRA,FRBp63@0|BF@6|//@9|FRA@11|FRBp@16|674@21|/@31|v2.05
771DFP Extract Biased Exponent X-formdxex FRT,FRB (Rc=0)|dxex. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|354@21|Rc@31|v2.05
772DFP Extract Biased Exponent Quad X-formdxexq FRT,FRBp (Rc=0)|dxexq. FRT,FRBp (Rc=1)63@0|FRT@6|///@11|FRBp@16|354@21|Rc@31|v2.05
773Floating Copy Sign X-formfcpsgn FRT, FRA, FRB (Rc=0)|fcpsgn. FRT, FRA, FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|8@21|Rc@31|v2.05
774Load Byte & Zero Caching Inhibited Indexed X-formlbzcix RT,RA,RB31@0|RT@6|RA@11|RB@16|853@21|/@31|v2.05
775Load Doubleword Caching Inhibited Indexed X-formldcix RT,RA,RB31@0|RT@6|RA@11|RB@16|885@21|/@31|v2.05
776Load Floating-Point Double Pair DS-formlfdp FRTp,DS(RA)57@0|FRTp@6|RA@11|DS@16|0@30|v2.05
777Load Floating-Point Double Pair Indexed X-formlfdpx FRTp,RA,RB31@0|FRTp@6|RA@11|RB@16|791@21|/@31|v2.05
778Load Floating-Point as Integer Word Algebraic Indexed X-formlfiwax FRT,RA,RB31@0|FRT@6|RA@11|RB@16|855@21|/@31|v2.05
779Load Halfword & Zero Caching Inhibited Indexed X-formlhzcix RT,RA,RB31@0|RT@6|RA@11|RB@16|821@21|/@31|v2.05
780Load Word & Zero Caching Inhibited Indexed X-formlwzcix RT,RA,RB31@0|RT@6|RA@11|RB@16|789@21|/@31|v2.05
781Parity Doubleword X-formprtyd RA,RS31@0|RS@6|RA@11|///@16|186@21|/@31|v2.05
782Parity Word X-formprtyw RA,RS31@0|RS@6|RA@11|///@16|154@21|/@31|v2.05
783SLB Find Entry ESID X-formslbfee. RT,RB31@0|RT@6|///@11|RB@16|979@21|1@31|v2.05
784Store Byte Caching Inhibited Indexed X-formstbcix RS,RA,RB31@0|RS@6|RA@11|RB@16|981@21|/@31|v2.05
785Store Doubleword Caching Inhibited Indexed X-formstdcix RS,RA,RB31@0|RS@6|RA@11|RB@16|1013@21|/@31|v2.05
786Store Floating-Point Double Pair DS-formstfdp FRSp,DS(RA)61@0|FRSp@6|RA@11|DS@16|0@30|v2.05
787Store Floating-Point Double Pair Indexed X-formstfdpx FRSp,RA,RB31@0|FRSp@6|RA@11|RB@16|919@21|/@31|v2.05
788Store Halfword Caching Inhibited Indexed X-formsthcix RS,RA,RB31@0|RS@6|RA@11|RB@16|949@21|/@31|v2.05
789Store Word Caching Inhibited Indexed X-formstwcix RS,RA,RB31@0|RS@6|RA@11|RB@16|917@21|/@31|v2.05
790Integer Select A-formisel RT,RA,RB,BC31@0|RT@6|RA@11|RB@16|BC@21|15@26|/@31|v2.03
791Load Vector Element Byte Indexed X-formlvebx VRT,RA,RB31@0|VRT@6|RA@11|RB@16|7@21|/@31|v2.03
792Load Vector Element Halfword Indexed X-formlvehx VRT,RA,RB31@0|VRT@6|RA@11|RB@16|39@21|/@31|v2.03
793Load Vector Element Word Indexed X-formlvewx VRT,RA,RB31@0|VRT@6|RA@11|RB@16|71@21|/@31|v2.03
794Load Vector for Shift Left Indexed X-formlvsl VRT,RA,RB31@0|VRT@6|RA@11|RB@16|6@21|/@31|v2.03
795Load Vector for Shift Right Indexed X-formlvsr VRT,RA,RB31@0|VRT@6|RA@11|RB@16|38@21|/@31|v2.03
796Load Vector Indexed X-formlvx VRT,RA,RB31@0|VRT@6|RA@11|RB@16|103@21|/@31|v2.03
797Load Vector Indexed Last X-formlvxl VRT,RA,RB31@0|VRT@6|RA@11|RB@16|359@21|/@31|v2.03
798Move From Vector Status and Control Register VX-formmfvscr VRT4@0|VRT@6|///@11|///@16|1540@21|v2.03
799Move To Vector Status and Control Register VX-formmtvscr VRB4@0|///@6|///@11|VRB@16|1604@21|v2.03
800Store Vector Element Byte Indexed X-formstvebx VRS,RA,RB31@0|VRS@6|RA@11|RB@16|135@21|/@31|v2.03
801Store Vector Element Halfword Indexed X-formstvehx VRS,RA,RB31@0|VRS@6|RA@11|RB@16|167@21|/@31|v2.03
802Store Vector Element Word Indexed X-formstvewx VRS,RA,RB31@0|VRS@6|RA@11|RB@16|199@21|/@31|v2.03
803Store Vector Indexed X-formstvx VRS,RA,RB31@0|VRS@6|RA@11|RB@16|231@21|/@31|v2.03
804Store Vector Indexed Last X-formstvxl VRS,RA,RB31@0|VRS@6|RA@11|RB@16|487@21|/@31|v2.03
805TLB Invalidate Entry Local X-formtlbiel RB,RS,RIC,PRS,R31@0|RS@6|/@11|RIC@12|PRS@14|R@15|RB@16|274@21|/@31|v2.03
806Vector Add & write Carry Unsigned Word VX-formvaddcuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|384@21|v2.03
807Vector Add Floating-Point VX-formvaddfp VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|10@21|v2.03
808Vector Add Signed Byte Saturate VX-formvaddsbs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|768@21|v2.03
809Vector Add Signed Halfword Saturate VX-formvaddshs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|832@21|v2.03
810Vector Add Signed Word Saturate VX-formvaddsws VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|896@21|v2.03
811Vector Add Unsigned Byte Modulo VX-formvaddubm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|0@21|v2.03
812Vector Add Unsigned Byte Saturate VX-formvaddubs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|512@21|v2.03
813Vector Add Unsigned Halfword Modulo VX-formvadduhm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|64@21|v2.03
814Vector Add Unsigned Halfword Saturate VX-formvadduhs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|576@21|v2.03
815Vector Add Unsigned Word Modulo VX-formvadduwm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|128@21|v2.03
816Vector Add Unsigned Word Saturate VX-formvadduws VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|640@21|v2.03
817Vector Logical AND VX-formvand VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1028@21|v2.03
818Vector Logical AND with Complement VX-formvandc VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1092@21|v2.03
819Vector Average Signed Byte VX-formvavgsb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1282@21|v2.03
820Vector Average Signed Halfword VX-formvavgsh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1346@21|v2.03
821Vector Average Signed Word VX-formvavgsw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1410@21|v2.03
822Vector Average Unsigned Byte VX-formvavgub VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1026@21|v2.03
823Vector Average Unsigned Halfword VX-formvavguh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1090@21|v2.03
824Vector Average Unsigned Word VX-formvavguw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1154@21|v2.03
825Vector Convert with round to nearest From Signed Word to floating-point format VX-formvcfsx VRT,VRB,UIM4@0|VRT@6|UIM@11|VRB@16|842@21|v2.03
826Vector Convert with round to nearest From Unsigned Word to floating-point format VX-formvcfux VRT,VRB,UIM4@0|VRT@6|UIM@11|VRB@16|778@21|v2.03
827Vector Compare Bounds Floating-Point VC-formvcmpbfp VRT,VRA,VRB (Rc=0)|vcmpbfp. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|966@22|v2.03
828Vector Compare Equal Floating-Point VC-formvcmpeqfp VRT,VRA,VRB (Rc=0)|vcmpeqfp. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|198@22|v2.03
829Vector Compare Equal Unsigned Byte VC-formvcmpequb VRT,VRA,VRB (Rc=0)|vcmpequb. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|6@22|v2.03
830Vector Compare Equal Unsigned Halfword VC-formvcmpequh VRT,VRA,VRB (Rc=0)|vcmpequh. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|70@22|v2.03
831Vector Compare Equal Unsigned Word VC-formvcmpequw VRT,VRA,VRB (Rc=0)|vcmpequw. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|134@22|v2.03
832Vector Compare Greater Than or Equal Floating-Point VC-formvcmpgefp VRT,VRA,VRB (Rc=0)|vcmpgefp. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|454@22|v2.03
833Vector Compare Greater Than Floating-Point VC-formvcmpgtfp VRT,VRA,VRB (Rc=0)|vcmpgtfp. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|710@22|v2.03
834Vector Compare Greater Than Signed Byte VC-formvcmpgtsb VRT,VRA,VRB (Rc=0)|vcmpgtsb. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|774@22|v2.03
835Vector Compare Greater Than Signed Halfword VC-formvcmpgtsh VRT,VRA,VRB (Rc=0)|vcmpgtsh. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|838@22|v2.03
836Vector Compare Greater Than Signed Word VC-formvcmpgtsw VRT,VRA,VRB (Rc=0)|vcmpgtsw. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|902@22|v2.03
837Vector Compare Greater Than Unsigned Byte VC-formvcmpgtub VRT,VRA,VRB (Rc=0)|vcmpgtub. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|518@22|v2.03
838Vector Compare Greater Than Unsigned Halfword VC-formvcmpgtuh VRT,VRA,VRB (Rc=0)|vcmpgtuh. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|582@22|v2.03
839Vector Compare Greater Than Unsigned Word VC-formvcmpgtuw VRT,VRA,VRB (Rc=0)|vcmpgtuw. VRT,VRA,VRB (Rc=1)4@0|VRT@6|VRA@11|VRB@16|Rc@21|646@22|v2.03
840Vector Convert with round to zero from floating-point To Signed Word format Saturate VX-formvctsxs VRT,VRB,UIM4@0|VRT@6|UIM@11|VRB@16|970@21|v2.03
841Vector Convert with round to zero from floating-point To Unsigned Word format Saturate VX-formvctuxs VRT,VRB,UIM4@0|VRT@6|UIM@11|VRB@16|906@21|v2.03
842Vector 2 Raised to the Exponent Estimate Floating-Point VX-formvexptefp VRT,VRB4@0|VRT@6|///@11|VRB@16|394@21|v2.03
843Vector Log Base 2 Estimate Floating-Point VX-formvlogefp VRT,VRB4@0|VRT@6|///@11|VRB@16|458@21|v2.03
844Vector Multiply-Add Floating-Point VA-formvmaddfp VRT,VRA,VRC,VRB4@0|VRT@6|VRA@11|VRB@16|VRC@21|46@26|v2.03
845Vector Maximum Floating-Point VX-formvmaxfp VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1034@21|v2.03
846Vector Maximum Signed Byte VX-formvmaxsb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|258@21|v2.03
847Vector Maximum Signed Halfword VX-formvmaxsh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|322@21|v2.03
848Vector Maximum Signed Word VX-formvmaxsw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|386@21|v2.03
849Vector Maximum Unsigned Byte VX-formvmaxub VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|2@21|v2.03
850Vector Maximum Unsigned Halfword VX-formvmaxuh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|66@21|v2.03
851Vector Maximum Unsigned Word VX-formvmaxuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|130@21|v2.03
852Vector Multiply-High-Add Signed Halfword Saturate VA-formvmhaddshs VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|32@26|v2.03
853Vector Multiply-High-Round-Add Signed Halfword Saturate VA-formvmhraddshs VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|33@26|v2.03
854Vector Minimum Floating-Point VX-formvminfp VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1098@21|v2.03
855Vector Minimum Signed Byte VX-formvminsb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|770@21|v2.03
856Vector Minimum Signed Halfword VX-formvminsh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|834@21|v2.03
857Vector Minimum Signed Word VX-formvminsw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|898@21|v2.03
858Vector Minimum Unsigned Byte VX-formvminub VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|514@21|v2.03
859Vector Minimum Unsigned Halfword VX-formvminuh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|578@21|v2.03
860Vector Minimum Unsigned Word VX-formvminuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|642@21|v2.03
861Vector Multiply-Low-Add Unsigned Halfword Modulo VA-formvmladduhm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|34@26|v2.03
862Vector Merge High Byte VX-formvmrghb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|12@21|v2.03
863Vector Merge High Halfword VX-formvmrghh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|76@21|v2.03
864Vector Merge High Word VX-formvmrghw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|140@21|v2.03
865Vector Merge Low Byte VX-formvmrglb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|268@21|v2.03
866Vector Merge Low Halfword VX-formvmrglh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|332@21|v2.03
867Vector Merge Low Word VX-formvmrglw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|396@21|v2.03
868Vector Multiply-Sum Mixed Byte Modulo VA-formvmsummbm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|37@26|v2.03
869Vector Multiply-Sum Signed Halfword Modulo VA-formvmsumshm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|40@26|v2.03
870Vector Multiply-Sum Signed Halfword Saturate VA-formvmsumshs VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|41@26|v2.03
871Vector Multiply-Sum Unsigned Byte Modulo VA-formvmsumubm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|36@26|v2.03
872Vector Multiply-Sum Unsigned Halfword Modulo VA-formvmsumuhm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|38@26|v2.03
873Vector Multiply-Sum Unsigned Halfword Saturate VA-formvmsumuhs VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|39@26|v2.03
874Vector Multiply Even Signed Byte VX-formvmulesb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|776@21|v2.03
875Vector Multiply Even Signed Halfword VX-formvmulesh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|840@21|v2.03
876Vector Multiply Even Unsigned Byte VX-formvmuleub VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|520@21|v2.03
877Vector Multiply Even Unsigned Halfword VX-formvmuleuh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|584@21|v2.03
878Vector Multiply Odd Signed Byte VX-formvmulosb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|264@21|v2.03
879Vector Multiply Odd Signed Halfword VX-formvmulosh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|328@21|v2.03
880Vector Multiply Odd Unsigned Byte VX-formvmuloub VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|8@21|v2.03
881Vector Multiply Odd Unsigned Halfword VX-formvmulouh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|72@21|v2.03
882Vector Negative Multiply-Subtract Floating-Point VA-formvnmsubfp VRT,VRA,VRC,VRB4@0|VRT@6|VRA@11|VRB@16|VRC@21|47@26|v2.03
883Vector Logical NOR VX-formvnor VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1284@21|v2.03
884Vector Logical OR VX-formvor VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1156@21|v2.03
885Vector Permute VA-formvperm VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|43@26|v2.03
886Vector Pack Pixel VX-formvpkpx VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|782@21|v2.03
887Vector Pack Signed Halfword Signed Saturate VX-formvpkshss VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|398@21|v2.03
888Vector Pack Signed Halfword Unsigned Saturate VX-formvpkshus VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|270@21|v2.03
889Vector Pack Signed Word Signed Saturate VX-formvpkswss VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|462@21|v2.03
890Vector Pack Signed Word Unsigned Saturate VX-formvpkswus VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|334@21|v2.03
891Vector Pack Unsigned Halfword Unsigned Modulo VX-formvpkuhum VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|14@21|v2.03
892Vector Pack Unsigned Halfword Unsigned Saturate VX-formvpkuhus VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|142@21|v2.03
893Vector Pack Unsigned Word Unsigned Modulo VX-formvpkuwum VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|78@21|v2.03
894Vector Pack Unsigned Word Unsigned Saturate VX-formvpkuwus VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|206@21|v2.03
895Vector Reciprocal Estimate Floating-Point VX-formvrefp VRT,VRB4@0|VRT@6|///@11|VRB@16|266@21|v2.03
896Vector Round to Floating-Point Integer toward -Infinity VX-formvrfim VRT,VRB4@0|VRT@6|///@11|VRB@16|714@21|v2.03
897Vector Round to Floating-Point Integer Nearest VX-formvrfin VRT,VRB4@0|VRT@6|///@11|VRB@16|522@21|v2.03
898Vector Round to Floating-Point Integer toward +Infinity VX-formvrfip VRT,VRB4@0|VRT@6|///@11|VRB@16|650@21|v2.03
899Vector Round to Floating-Point Integer toward Zero VX-formvrfiz VRT,VRB4@0|VRT@6|///@11|VRB@16|586@21|v2.03
900Vector Rotate Left Byte VX-formvrlb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|4@21|v2.03
901Vector Rotate Left Halfword VX-formvrlh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|68@21|v2.03
902Vector Rotate Left Word VX-formvrlw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|132@21|v2.03
903Vector Reciprocal Square Root Estimate Floating-Point VX-formvrsqrtefp VRT,VRB4@0|VRT@6|///@11|VRB@16|330@21|v2.03
904Vector Select VA-formvsel VRT,VRA,VRB,VRC4@0|VRT@6|VRA@11|VRB@16|VRC@21|42@26|v2.03
905Vector Shift Left VX-formvsl VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|452@21|v2.03
906Vector Shift Left Byte VX-formvslb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|260@21|v2.03
907Vector Shift Left Double by Octet Immediate VA-formvsldoi VRT,VRA,VRB,SHB4@0|VRT@6|VRA@11|VRB@16|/@21|SHB@22|44@26|v2.03
908Vector Shift Left Halfword VX-formvslh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|324@21|v2.03
909Vector Shift Left by Octet VX-formvslo VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1036@21|v2.03
910Vector Shift Left Word VX-formvslw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|388@21|v2.03
911Vector Splat Byte VX-formvspltb VRT,VRB,UIM4@0|VRT@6|/@11|UIM@12|VRB@16|524@21|v2.03
912Vector Splat Halfword VX-formvsplth VRT,VRB,UIM4@0|VRT@6|//@11|UIM@13|VRB@16|588@21|v2.03
913Vector Splat Immediate Signed Byte VX-formvspltisb VRT,SIM4@0|VRT@6|SIM@11|///@16|780@21|v2.03
914Vector Splat Immediate Signed Halfword VX-formvspltish VRT,SIM4@0|VRT@6|SIM@11|///@16|844@21|v2.03
915Vector Splat Immediate Signed Word VX-formvspltisw VRT,SIM4@0|VRT@6|SIM@11|///@16|908@21|v2.03
916Vector Splat Word VX-formvspltw VRT,VRB,UIM4@0|VRT@6|///@11|UIM@14|VRB@16|652@21|v2.03
917Vector Shift Right VX-formvsr VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|708@21|v2.03
918Vector Shift Right Algebraic Byte VX-formvsrab VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|772@21|v2.03
919Vector Shift Right Algebraic Halfword VX-formvsrah VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|836@21|v2.03
920Vector Shift Right Algebraic Word VX-formvsraw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|900@21|v2.03
921Vector Shift Right Byte VX-formvsrb VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|516@21|v2.03
922Vector Shift Right Halfword VX-formvsrh VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|580@21|v2.03
923Vector Shift Right by Octet VX-formvsro VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1100@21|v2.03
924Vector Shift Right Word VX-formvsrw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|644@21|v2.03
925Vector Subtract & Write Carry-out Unsigned Word VX-formvsubcuw VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1408@21|v2.03
926Vector Subtract Floating-Point VX-formvsubfp VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|74@21|v2.03
927Vector Subtract Signed Byte Saturate VX-formvsubsbs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1792@21|v2.03
928Vector Subtract Signed Halfword Saturate VX-formvsubshs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1856@21|v2.03
929Vector Subtract Signed Word Saturate VX-formvsubsws VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1920@21|v2.03
930Vector Subtract Unsigned Byte Modulo VX-formvsububm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1024@21|v2.03
931Vector Subtract Unsigned Byte Saturate VX-formvsububs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1536@21|v2.03
932Vector Subtract Unsigned Halfword Modulo VX-formvsubuhm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1088@21|v2.03
933Vector Subtract Unsigned Halfword Saturate VX-formvsubuhs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1600@21|v2.03
934Vector Subtract Unsigned Word Modulo VX-formvsubuwm VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1152@21|v2.03
935Vector Subtract Unsigned Word Saturate VX-formvsubuws VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1664@21|v2.03
936Vector Sum across Half Signed Word Saturate VX-formvsum2sws VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1672@21|v2.03
937Vector Sum across Quarter Signed Byte Saturate VX-formvsum4sbs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1800@21|v2.03
938Vector Sum across Quarter Signed Halfword Saturate VX-formvsum4shs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1608@21|v2.03
939Vector Sum across Quarter Unsigned Byte Saturate VX-formvsum4ubs VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1544@21|v2.03
940Vector Sum across Signed Word Saturate VX-formvsumsws VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1928@21|v2.03
941Vector Unpack High Pixel VX-formvupkhpx VRT,VRB4@0|VRT@6|///@11|VRB@16|846@21|v2.03
942Vector Unpack High Signed Byte VX-formvupkhsb VRT,VRB4@0|VRT@6|///@11|VRB@16|526@21|v2.03
943Vector Unpack High Signed Halfword VX-formvupkhsh VRT,VRB4@0|VRT@6|///@11|VRB@16|590@21|v2.03
944Vector Unpack Low Pixel VX-formvupklpx VRT,VRB4@0|VRT@6|///@11|VRB@16|974@21|v2.03
945Vector Unpack Low Signed Byte VX-formvupklsb VRT,VRB4@0|VRT@6|///@11|VRB@16|654@21|v2.03
946Vector Unpack Low Signed Halfword VX-formvupklsh VRT,VRB4@0|VRT@6|///@11|VRB@16|718@21|v2.03
947Vector Logical XOR VX-formvxor VRT,VRA,VRB4@0|VRT@6|VRA@11|VRB@16|1220@21|v2.03
948Floating Reciprocal Estimate A-formfre FRT,FRB (Rc=0)|fre. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|///@21|24@26|Rc@31|v2.02
949Floating Round to Integer Minus X-formfrim FRT,FRB (Rc=0)|frim. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|488@21|Rc@31|v2.02
950Floating Round to Integer Nearest X-formfrin FRT,FRB (Rc=0)|frin. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|392@21|Rc@31|v2.02
951Floating Round to Integer Plus X-formfrip FRT,FRB (Rc=0)|frip. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|456@21|Rc@31|v2.02
952Floating Round to Integer Toward Zero X-formfriz FRT,FRB (Rc=0)|friz. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|424@21|Rc@31|v2.02
953Floating Reciprocal Square Root Estimate Single A-formfrsqrtes FRT,FRB (Rc=0)|frsqrtes. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|///@21|26@26|Rc@31|v2.02
954Return From Interrupt Doubleword Hypervisor XL-formhrfid19@0|///@6|///@11|///@16|274@21|/@31|v2.02
955Population Count Bytes X-formpopcntb RA, RS31@0|RS@6|RA@11|///@16|122@21|/@31|v2.02
956Move From One Condition Register Field XFX-formmfocrf RT,FXM31@0|RT@6|1@11|FXM@12|/@20|19@21|/@31|v2.01
957Move To One Condition Register Field XFX-formmtocrf FXM,RS31@0|RS@6|1@11|FXM@12|/@20|144@21|/@31|v2.01
958SLB Move From Entry ESID X-formslbmfee RT,RB31@0|RT@6|///@11|L@15|RB@16|915@21|/@31|v2.00
959SLB Move From Entry VSID X-formslbmfev RT,RB31@0|RT@6|///@11|L@15|RB@16|851@21|/@31|v2.00
960SLB Move To Entry X-formslbmte RS,RB31@0|RS@6|///@11|RB@16|402@21|/@31|v2.00
961Return From System Call Vectored XL-formrfscv19@0|///@6|///@11|///@16|82@21|/@31|v3.0
962System Call Vectored SC-formscv LEV17@0|///@6|///@11|///@16|LEV@20|///@27|0@30|1@31|v3.0
963Load Quadword DQ-formlq RTp,DQ(RA)56@0|RTp@6|RA@11|DQ@16|///@28|v2.03
964Store Quadword DS-formstq RSp,DS(RA)62@0|RSp@6|RA@11|DS@16|2@30|v2.03
965Count Leading Zeros Doubleword X-formcntlzd RA,RS (Rc=0)|cntlzd. RA,RS (Rc=1)31@0|RS@6|RA@11|///@16|58@21|Rc@31|PPC
966Data Cache Block Flush X-formdcbf RA,RB,L31@0|//@6|L@8|RA@11|RB@16|86@21|/@31|PPC
967Data Cache Block Store X-formdcbst RA,RB31@0|///@6|RA@11|RB@16|54@21|/@31|PPC
968Data Cache Block Touch X-formdcbt RA,RB,TH31@0|TH@6|RA@11|RB@16|278@21|/@31|PPC
969Data Cache Block Touch for Store X-formdcbtst RA,RB,TH31@0|TH@6|RA@11|RB@16|246@21|/@31|PPC
970Divide Doubleword XO-formdivd RT,RA,RB (OE=0 Rc=0)|divd. RT,RA,RB (OE=0 Rc=1)|divdo RT,RA,RB (OE=1 Rc=0)|divdo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|489@22|Rc@31|PPC
971Divide Doubleword Unsigned XO-formdivdu RT,RA,RB (OE=0 Rc=0)|divdu. RT,RA,RB (OE=0 Rc=1)|divduo RT,RA,RB (OE=1 Rc=0)|divduo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|457@22|Rc@31|PPC
972Divide Word XO-formdivw RT,RA,RB (OE=0 Rc=0)|divw. RT,RA,RB (OE=0 Rc=1)|divwo RT,RA,RB (OE=1 Rc=0)|divwo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|491@22|Rc@31|PPC
973Divide Word Unsigned XO-formdivwu RT,RA,RB (OE=0 Rc=0)|divwu. RT,RA,RB (OE=0 Rc=1)|divwuo RT,RA,RB (OE=1 Rc=0)|divwuo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|459@22|Rc@31|PPC
974Enforce In-order Execution of I/O X-formeieio31@0|///@6|///@11|///@16|854@21|/@31|PPC
975Extend Sign Byte X-formextsb RA,RS (Rc=0)|extsb. RA,RS (Rc=1)31@0|RS@6|RA@11|///@16|954@21|Rc@31|PPC
976Extend Sign Word X-formextsw RA,RS (Rc=0)|extsw. RA,RS (Rc=1)31@0|RS@6|RA@11|///@16|986@21|Rc@31|PPC
977Floating Add Single A-formfadds FRT,FRA,FRB (Rc=0)|fadds. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|///@21|21@26|Rc@31|PPC
978Floating Convert with round Signed Doubleword to Double-Precision format X-formfcfid FRT,FRB (Rc=0)|fcfid. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|846@21|Rc@31|PPC
979Floating Convert with round Double-Precision To Signed Doubleword format X-formfctid FRT,FRB (Rc=0)|fctid. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|814@21|Rc@31|PPC
980Floating Convert with truncate Double-Precision To Signed Doubleword format X-formfctidz FRT,FRB (Rc=0)|fctidz. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|815@21|Rc@31|PPC
981Floating Divide Single A-formfdivs FRT,FRA,FRB (Rc=0)|fdivs. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|///@21|18@26|Rc@31|PPC
982Floating Multiply-Add Single A-formfmadds FRT,FRA,FRC,FRB (Rc=0)|fmadds. FRT,FRA,FRC,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|FRC@21|29@26|Rc@31|PPC
983Floating Multiply-Subtract Single A-formfmsubs FRT,FRA,FRC,FRB (Rc=0)|fmsubs. FRT,FRA,FRC,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|FRC@21|28@26|Rc@31|PPC
984Floating Multiply Single A-formfmuls FRT,FRA,FRC (Rc=0)|fmuls. FRT,FRA,FRC (Rc=1)59@0|FRT@6|FRA@11|///@16|FRC@21|25@26|Rc@31|PPC
985Floating Negative Multiply-Add Single A-formfnmadds FRT,FRA,FRC,FRB (Rc=0)|fnmadds. FRT,FRA,FRC,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|FRC@21|31@26|Rc@31|PPC
986Floating Negative Multiply-Subtract Single A-formfnmsubs FRT,FRA,FRC,FRB (Rc=0)|fnmsubs. FRT,FRA,FRC,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|FRC@21|30@26|Rc@31|PPC
987Floating Reciprocal Estimate Single A-formfres FRT,FRB (Rc=0)|fres. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|///@21|24@26|Rc@31|PPC
988Floating Reciprocal Square Root Estimate A-formfrsqrte FRT,FRB (Rc=0)|frsqrte. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|///@21|26@26|Rc@31|PPC
989Floating Select A-formfsel FRT,FRA,FRC,FRB (Rc=0)|fsel. FRT,FRA,FRC,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|FRC@21|23@26|Rc@31|PPC
990Floating Square Root Single A-formfsqrts FRT,FRB (Rc=0)|fsqrts. FRT,FRB (Rc=1)59@0|FRT@6|///@11|FRB@16|///@21|22@26|Rc@31|PPC
991Floating Subtract Single A-formfsubs FRT,FRA,FRB (Rc=0)|fsubs. FRT,FRA,FRB (Rc=1)59@0|FRT@6|FRA@11|FRB@16|///@21|20@26|Rc@31|PPC
992Instruction Cache Block Invalidate X-formicbi RA,RB31@0|///@6|RA@11|RB@16|982@21|/@31|PPC
993Load Doubleword DS-formld RT,DS(RA)58@0|RT@6|RA@11|DS@16|0@30|PPC
994Load Doubleword And Reserve Indexed X-formldarx RT,RA,RB,EH31@0|RT@6|RA@11|RB@16|84@21|EH@31|PPC
995Load Doubleword with Update DS-formldu RT,DS(RA)58@0|RT@6|RA@11|DS@16|1@30|PPC
996Load Doubleword with Update Indexed X-formldux RT,RA,RB31@0|RT@6|RA@11|RB@16|53@21|/@31|PPC
997Load Doubleword Indexed X-formldx RT,RA,RB31@0|RT@6|RA@11|RB@16|21@21|/@31|PPC
998Load Word Algebraic DS-formlwa RT,DS(RA)58@0|RT@6|RA@11|DS@16|2@30|PPC
999Load Word & Reserve Indexed X-formlwarx RT,RA,RB,EH31@0|RT@6|RA@11|RB@16|20@21|EH@31|PPC
1000Load Word Algebraic with Update Indexed X-formlwaux RT,RA,RB31@0|RT@6|RA@11|RB@16|373@21|/@31|PPC
1001Load Word Algebraic Indexed X-formlwax RT,RA,RB31@0|RT@6|RA@11|RB@16|341@21|/@31|PPC
1002Move From Time Base XFX-formmftb RT,TBR31@0|RT@6|tbr@11|371@21|/@31|PPC
1003Move To MSR Doubleword X-formmtmsrd RS,L31@0|RS@6|///@11|L@15|///@16|178@21|/@31|PPC
1004Multiply High Doubleword XO-formmulhd RT,RA,RB (Rc=0)|mulhd. RT,RA,RB (Rc=1)31@0|RT@6|RA@11|RB@16|/@21|73@22|Rc@31|PPC
1005Multiply High Doubleword Unsigned XO-formmulhdu RT,RA,RB (Rc=0)|mulhdu. RT,RA,RB (Rc=1)31@0|RT@6|RA@11|RB@16|/@21|9@22|Rc@31|PPC
1006Multiply High Word XO-formmulhw RT,RA,RB (Rc=0)|mulhw. RT,RA,RB (Rc=1)31@0|RT@6|RA@11|RB@16|/@21|75@22|Rc@31|PPC
1007Multiply High Word Unsigned XO-formmulhwu RT,RA,RB (Rc=0)|mulhwu. RT,RA,RB (Rc=1)31@0|RT@6|RA@11|RB@16|/@21|11@22|Rc@31|PPC
1008Multiply Low Doubleword XO-formmulld RT,RA,RB (OE=0 Rc=0)|mulld. RT,RA,RB (OE=0 Rc=1)|mulldo RT,RA,RB (OE=1 Rc=0)|mulldo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|233@22|Rc@31|PPC
1009Return from Interrupt Doubleword XL-formrfid19@0|///@6|///@11|///@16|18@21|/@31|PPC
1010Rotate Left Doubleword then Clear Left MDS-formrldcl RA,RS,RB,MB (Rc=0)|rldcl. RA,RS,RB,MB (Rc=1)30@0|RS@6|RA@11|RB@16|mb@21|8@27|Rc@31|PPC
1011Rotate Left Doubleword then Clear Right MDS-formrldcr RA,RS,RB,ME (Rc=0)|rldcr. RA,RS,RB,ME (Rc=1)30@0|RS@6|RA@11|RB@16|me@21|9@27|Rc@31|PPC
1012Rotate Left Doubleword Immediate then Clear MD-formrldic RA,RS,SH,MB (Rc=0)|rldic. RA,RS,SH,MB (Rc=1)30@0|RS@6|RA@11|sh@16|mb@21|2@27|sh@30|Rc@31|PPC
1013Rotate Left Doubleword Immediate then Clear Left MD-formrldicl RA,RS,SH,MB (Rc=0)|rldicl. RA,RS,SH,MB (Rc=1)30@0|RS@6|RA@11|sh@16|mb@21|0@27|sh@30|Rc@31|PPC
1014Rotate Left Doubleword Immediate then Clear Right MD-formrldicr RA,RS,SH,ME (Rc=0)|rldicr. RA,RS,SH,ME (Rc=1)30@0|RS@6|RA@11|sh@16|me@21|1@27|sh@30|Rc@31|PPC
1015Rotate Left Doubleword Immediate then Mask Insert MD-formrldimi RA,RS,SH,MB (Rc=0)|rldimi. RA,RS,SH,MB (Rc=1)30@0|RS@6|RA@11|sh@16|mb@21|3@27|sh@30|Rc@31|PPC
1016System Call SC-formsc LEV17@0|///@6|///@11|///@16|LEV@20|///@27|1@30|/@31|PPC
1017SLB Invalidate All X-formslbia IH31@0|//@6|IH@8|///@11|///@16|498@21|/@31|PPC
1018SLB Invalidate Entry X-formslbie RB31@0|///@6|///@11|RB@16|434@21|/@31|PPC
1019Shift Left Doubleword X-formsld RA,RS,RB (Rc=0)|sld. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|27@21|Rc@31|PPC
1020Shift Right Algebraic Doubleword X-formsrad RA,RS,RB (Rc=0)|srad. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|794@21|Rc@31|PPC
1021Shift Right Algebraic Doubleword Immediate XS-formsradi RA,RS,SH (Rc=0)|sradi. RA,RS,SH (Rc=1)31@0|RS@6|RA@11|sh@16|413@21|sh@30|Rc@31|PPC
1022Shift Right Doubleword X-formsrd RA,RS,RB (Rc=0)|srd. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|539@21|Rc@31|PPC
1023Store Doubleword DS-formstd RS,DS(RA)62@0|RS@6|RA@11|DS@16|0@30|PPC
1024Store Doubleword Conditional Indexed X-formstdcx. RS,RA,RB31@0|RS@6|RA@11|RB@16|214@21|1@31|PPC
1025Store Doubleword with Update DS-formstdu RS,DS(RA)62@0|RS@6|RA@11|DS@16|1@30|PPC
1026Store Doubleword with Update Indexed X-formstdux RS,RA,RB31@0|RS@6|RA@11|RB@16|181@21|/@31|PPC
1027Store Doubleword Indexed X-formstdx RS,RA,RB31@0|RS@6|RA@11|RB@16|149@21|/@31|PPC
1028Store Floating-Point as Integer Word Indexed X-formstfiwx FRS,RA,RB31@0|FRS@6|RA@11|RB@16|983@21|/@31|PPC
1029Store Word Conditional Indexed X-formstwcx. RS,RA,RB31@0|RS@6|RA@11|RB@16|150@21|1@31|PPC
1030Subtract From XO-formsubf RT,RA,RB (OE=0 Rc=0)|subf. RT,RA,RB (OE=0 Rc=1)|subfo RT,RA,RB (OE=1 Rc=0)|subfo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|40@22|Rc@31|PPC
1031Trap Doubleword X-formtd TO,RA,RB31@0|TO@6|RA@11|RB@16|68@21|/@31|PPC
1032Trap Doubleword Immediate D-formtdi TO,RA,SI2@0|TO@6|RA@11|SI@16|PPC
1033TLB Synchronize X-formtlbsync31@0|///@6|///@11|///@16|566@21|/@31|PPC
1034Floating Convert with round Double-Precision To Signed Word format X-formfctiw FRT,FRB (Rc=0)|fctiw. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|14@21|Rc@31|P2
1035Floating Convert with truncate Double-Precision To Signed Word fomat X-formfctiwz FRT,FRB (Rc=0)|fctiwz. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|15@21|Rc@31|P2
1036Floating Square Root A-formfsqrt FRT,FRB (Rc=0)|fsqrt. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|///@21|22@26|Rc@31|P2
1037Add XO-formadd RT,RA,RB (OE=0 Rc=0)|add. RT,RA,RB (OE=0 Rc=1)|addo RT,RA,RB (OE=1 Rc=0)|addo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|266@22|Rc@31|P1
1038Add Carrying XO-formaddc RT,RA,RB (OE=0 Rc=0)|addc. RT,RA,RB (OE=0 Rc=1)|addco RT,RA,RB (OE=1 Rc=0)|addco. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|10@22|Rc@31|P1
1039Add Extended XO-formadde RT,RA,RB (OE=0 Rc=0)|adde. RT,RA,RB (OE=0 Rc=1)|addeo RT,RA,RB (OE=1 Rc=0)|addeo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|138@22|Rc@31|P1
1040Add Immediate D-formaddi RT,RA,SI|li RT,SI (RA=0)14@0|RT@6|RA@11|SI@16|P1
1041Add Immediate Carrying D-formaddic RT,RA,SI12@0|RT@6|RA@11|SI@16|P1
1042Add Immediate Carrying and Record D-formaddic. RT,RA,SI13@0|RT@6|RA@11|SI@16|P1
1043Add Immediate Shifted D-formaddis RT,RA,SI|lis RT,SI (RA=0)15@0|RT@6|RA@11|SI@16|P1
1044Add to Minus One Extended XO-formaddme RT,RA (OE=0 Rc=0)|addme. RT,RA (OE=0 Rc=1)|addmeo RT,RA (OE=1 Rc=0)|addmeo. RT,RA (OE=1 Rc=1)31@0|RT@6|RA@11|///@16|OE@21|234@22|Rc@31|P1
1045Add to Zero Extended XO-formaddze RT,RA (OE=0 Rc=0)|addze. RT,RA (OE=0 Rc=1)|addzeo RT,RA (OE=1 Rc=0)|addzeo. RT,RA (OE=1 Rc=1)31@0|RT@6|RA@11|///@16|OE@21|202@22|Rc@31|P1
1046AND X-formand RA,RS,RB (Rc=0)|and. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|28@21|Rc@31|P1
1047AND with Complement X-formandc RA,RS,RB (Rc=0)|andc. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|60@21|Rc@31|P1
1048AND Immediate D-formandi. RA,RS,UI28@0|RS@6|RA@11|UI@16|P1
1049AND Immediate Shifted D-formandis. RA,RS,UI29@0|RS@6|RA@11|UI@16|P1
1050Branch I-formb target_addr (AA=0 LK=0)|ba target_addr (AA=1 LK=0)|bl target_addr (AA=0 LK=1)|bla target_addr (AA=1 LK=1)18@0|LI@6|AA@30|LK@31|P1
1051Branch Conditional B-formbc BO,BI,target_addr (AA=0 LK=0)|bca BO,BI,target_addr (AA=1 LK=0)|bcl BO,BI,target_addr (AA=0 LK=1)|bcla BO,BI,target_addr (AA=1 LK=1)16@0|BO@6|BI@11|BD@16|AA@30|LK@31|P1
1052Branch Conditional to Count Register XL-formbcctr BO,BI,BH (LK=0)|bcctrl BO,BI,BH (LK=1)19@0|BO@6|BI@11|///@16|BH@19|528@21|LK@31|P1
1053Branch Conditional to Link Register XL-formbclr BO,BI,BH (LK=0)|bclrl BO,BI,BH (LK=1)19@0|BO@6|BI@11|///@16|BH@19|16@21|LK@31|P1
1054Compare X-formcmp BF,L,RA,RB|cmpw BF,RA,RB (L=0)|cmpd BF,RA,RB (L=1)31@0|BF@6|/@9|L@10|RA@11|RB@16|0@21|/@31|P1
1055Compare Immediate D-formcmpi BF,L,RA,SI|cmpwi BF,RA,SI (L=0)|cmpdi BF,RA,SI (L=1)11@0|BF@6|/@9|L@10|RA@11|SI@16|P1
1056Compare Logical X-formcmpl BF,L,RA,RB|cmplw BF,RA,RB (L=0)|cmpld BF,RA,RB (L=1)31@0|BF@6|/@9|L@10|RA@11|RB@16|32@21|/@31|P1
1057Compare Logical Immediate D-formcmpli BF,L,RA,UI|cmplwi BF,RA,UI (L=0)|cmpldi BF,RA,UI (L=1)10@0|BF@6|/@9|L@10|RA@11|UI@16|P1
1058Count Leading Zeros Word X-formcntlzw RA,RS (Rc=0)|cntlzw. RA,RS (Rc=1)31@0|RS@6|RA@11|///@16|26@21|Rc@31|P1
1059Condition Register AND XL-formcrand BT,BA,BB19@0|BT@6|BA@11|BB@16|257@21|/@31|P1
1060Condition Register AND with Complement XL-formcrandc BT,BA,BB19@0|BT@6|BA@11|BB@16|129@21|/@31|P1
1061Condition Register Equivalent XL-formcreqv BT,BA,BB19@0|BT@6|BA@11|BB@16|289@21|/@31|P1
1062Condition Register NAND XL-formcrnand BT,BA,BB19@0|BT@6|BA@11|BB@16|225@21|/@31|P1
1063Condition Register NOR XL-formcrnor BT,BA,BB19@0|BT@6|BA@11|BB@16|33@21|/@31|P1
1064Condition Register OR XL-formcror BT,BA,BB19@0|BT@6|BA@11|BB@16|449@21|/@31|P1
1065Condition Register OR with Complement XL-formcrorc BT,BA,BB19@0|BT@6|BA@11|BB@16|417@21|/@31|P1
1066Condition Register XOR XL-formcrxor BT,BA,BB19@0|BT@6|BA@11|BB@16|193@21|/@31|P1
1067Data Cache Block set to Zero X-formdcbz RA,RB31@0|///@6|RA@11|RB@16|1014@21|/@31|P1
1068Equivalent X-formeqv RA,RS,RB (Rc=0)|eqv. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|284@21|Rc@31|P1
1069Extend Sign Halfword X-formextsh RA,RS (Rc=0)|extsh. RA,RS (Rc=1)31@0|RS@6|RA@11|///@16|922@21|Rc@31|P1
1070Floating Absolute Value X-formfabs FRT,FRB (Rc=0)|fabs. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|264@21|Rc@31|P1
1071Floating Add A-formfadd FRT,FRA,FRB (Rc=0)|fadd. FRT,FRA,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|///@21|21@26|Rc@31|P1
1072Floating Compare Ordered X-formfcmpo BF,FRA,FRB63@0|BF@6|//@9|FRA@11|FRB@16|32@21|/@31|P1
1073Floating Compare Unordered X-formfcmpu BF,FRA,FRB63@0|BF@6|//@9|FRA@11|FRB@16|0@21|/@31|P1
1074Floating Divide A-formfdiv FRT,FRA,FRB (Rc=0)|fdiv. FRT,FRA,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|///@21|18@26|Rc@31|P1
1075Floating Multiply-Add A-formfmadd FRT,FRA,FRC,FRB (Rc=0)|fmadd. FRT,FRA,FRC,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|FRC@21|29@26|Rc@31|P1
1076Floating Move Register X-formfmr FRT,FRB (Rc=0)|fmr. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|72@21|Rc@31|P1
1077Floating Multiply-Subtract A-formfmsub FRT,FRA,FRC,FRB (Rc=0)|fmsub. FRT,FRA,FRC,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|FRC@21|28@26|Rc@31|P1
1078Floating Multiply A-formfmul FRT,FRA,FRC (Rc=0)|fmul. FRT,FRA,FRC (Rc=1)63@0|FRT@6|FRA@11|///@16|FRC@21|25@26|Rc@31|P1
1079Floating Negative Absolute Value X-formfnabs FRT,FRB (Rc=0)|fnabs. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|136@21|Rc@31|P1
1080Floating Negate X-formfneg FRT,FRB (Rc=0)|fneg. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|40@21|Rc@31|P1
1081Floating Negative Multiply-Add A-formfnmadd FRT,FRA,FRC,FRB (Rc=0)|fnmadd. FRT,FRA,FRC,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|FRC@21|31@26|Rc@31|P1
1082Floating Negative Multiply-Subtract A-formfnmsub FRT,FRA,FRC,FRB (Rc=0)|fnmsub. FRT,FRA,FRC,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|FRC@21|30@26|Rc@31|P1
1083Floating Round to Single-Precision X-formfrsp FRT,FRB (Rc=0)|frsp. FRT,FRB (Rc=1)63@0|FRT@6|///@11|FRB@16|12@21|Rc@31|P1
1084Floating Subtract A-formfsub FRT,FRA,FRB (Rc=0)|fsub. FRT,FRA,FRB (Rc=1)63@0|FRT@6|FRA@11|FRB@16|///@21|20@26|Rc@31|P1
1085Instruction Synchronize XL-formisync19@0|///@6|///@11|///@16|150@21|/@31|P1
1086Load Byte and Zero D-formlbz RT,D(RA)34@0|RT@6|RA@11|D@16|P1
1087Load Byte and Zero with Update D-formlbzu RT,D(RA)35@0|RT@6|RA@11|D@16|P1
1088Load Byte and Zero with Update Indexed X-formlbzux RT,RA,RB31@0|RT@6|RA@11|RB@16|119@21|/@31|P1
1089Load Byte and Zero Indexed X-formlbzx RT,RA,RB31@0|RT@6|RA@11|RB@16|87@21|/@31|P1
1090Load Floating-Point Double D-formlfd FRT,D(RA)50@0|FRT@6|RA@11|D@16|P1
1091Load Floating-Point Double with Update D-formlfdu FRT,D(RA)51@0|FRT@6|RA@11|D@16|P1
1092Load Floating-Point Double with Update Indexed X-formlfdux FRT,RA,RB31@0|FRT@6|RA@11|RB@16|631@21|/@31|P1
1093Load Floating-Point Double Indexed X-formlfdx FRT,RA,RB31@0|FRT@6|RA@11|RB@16|599@21|/@31|P1
1094Load Floating-Point Single D-formlfs FRT,D(RA)48@0|FRT@6|RA@11|D@16|P1
1095Load Floating-Point Single with Update D-formlfsu FRT,D(RA)49@0|FRT@6|RA@11|D@16|P1
1096Load Floating-Point Single with Update Indexed X-formlfsux FRT,RA,RB31@0|FRT@6|RA@11|RB@16|567@21|/@31|P1
1097Load Floating-Point Single Indexed X-formlfsx FRT,RA,RB31@0|FRT@6|RA@11|RB@16|535@21|/@31|P1
1098Load Halfword Algebraic D-formlha RT,D(RA)42@0|RT@6|RA@11|D@16|P1
1099Load Halfword Algebraic with Update D-formlhau RT,D(RA)43@0|RT@6|RA@11|D@16|P1
1100Load Halfword Algebraic with Update Indexed X-formlhaux RT,RA,RB31@0|RT@6|RA@11|RB@16|375@21|/@31|P1
1101Load Halfword Algebraic Indexed X-formlhax RT,RA,RB31@0|RT@6|RA@11|RB@16|343@21|/@31|P1
1102Load Halfword Byte-Reverse Indexed X-formlhbrx RT,RA,RB31@0|RT@6|RA@11|RB@16|790@21|/@31|P1
1103Load Halfword and Zero D-formlhz RT,D(RA)40@0|RT@6|RA@11|D@16|P1
1104Load Halfword and Zero with Update D-formlhzu RT,D(RA)41@0|RT@6|RA@11|D@16|P1
1105Load Halfword and Zero with Update Indexed X-formlhzux RT,RA,RB31@0|RT@6|RA@11|RB@16|311@21|/@31|P1
1106Load Halfword and Zero Indexed X-formlhzx RT,RA,RB31@0|RT@6|RA@11|RB@16|279@21|/@31|P1
1107Load Multiple Word D-formlmw RT,D(RA)46@0|RT@6|RA@11|D@16|P1
1108Load String Word Immediate X-formlswi RT,RA,NB31@0|RT@6|RA@11|NB@16|597@21|/@31|P1
1109Load String Word Indexed X-formlswx RT,RA,RB31@0|RT@6|RA@11|RB@16|533@21|/@31|P1
1110Load Word Byte-Reverse Indexed X-formlwbrx RT,RA,RB31@0|RT@6|RA@11|RB@16|534@21|/@31|P1
1111Load Word and Zero D-formlwz RT,D(RA)32@0|RT@6|RA@11|D@16|P1
1112Load Word and Zero with Update D-formlwzu RT,D(RA)33@0|RT@6|RA@11|D@16|P1
1113Load Word and Zero with Update Indexed X-formlwzux RT,RA,RB31@0|RT@6|RA@11|RB@16|55@21|/@31|P1
1114Load Word and Zero Indexed X-formlwzx RT,RA,RB31@0|RT@6|RA@11|RB@16|23@21|/@31|P1
1115Move Condition Register Field XL-formmcrf BF,BFA19@0|BF@6|//@9|BFA@11|//@14|///@16|0@21|/@31|P1
1116Move to Condition Register from FPSCR X-formmcrfs BF,BFA63@0|BF@6|//@9|BFA@11|//@14|///@16|64@21|/@31|P1
1117Move From Condition Register XFX-formmfcr RT31@0|RT@6|0@11|///@12|/@20|19@21|/@31|P1
1118Move From FPSCR X-formmffs FRT (Rc=0)|mffs. FRT (Rc=1)63@0|FRT@6|0@11|///@16|583@21|Rc@31|P1
1119Move From MSR X-formmfmsr RT31@0|RT@6|///@11|///@16|83@21|/@31|P1
1120Move From Special Purpose Register XFX-formmfspr RT,SPR31@0|RT@6|spr@11|339@21|/@31|P1
1121Move To Condition Register Fields XFX-formmtcrf FXM,RS31@0|RS@6|0@11|FXM@12|/@20|144@21|/@31|P1
1122Move To FPSCR Bit 0 X-formmtfsb0 BT (Rc=0)|mtfsb0. BT (Rc=1)63@0|BT@6|///@11|///@16|70@21|Rc@31|P1
1123Move To FPSCR Bit 1 X-formmtfsb1 BT (Rc=0)|mtfsb1. BT (Rc=1)63@0|BT@6|///@11|///@16|38@21|Rc@31|P1
1124Move To FPSCR Fields XFL-formmtfsf FLM,FRB,L,W (Rc=0)|mtfsf. FLM,FRB,L,W (Rc=1)63@0|L@6|FLM@7|W@15|FRB@16|711@21|Rc@31|P1
1125Move To FPSCR Field Immediate X-formmtfsfi BF,U,W (Rc=0)|mtfsfi. BF,U,W (Rc=1)63@0|BF@6|//@9|///@11|W@15|U@16|/@20|134@21|Rc@31|P1
1126Move To MSR X-formmtmsr RS,L31@0|RS@6|///@11|L@15|///@16|146@21|/@31|P1
1127Move To Special Purpose Register XFX-formmtspr SPR,RS31@0|RS@6|spr@11|467@21|/@31|P1
1128Multiply Low Immediate D-formmulli RT,RA,SI7@0|RT@6|RA@11|SI@16|P1
1129Multiply Low Word XO-formmullw RT,RA,RB (OE=0 Rc=0)|mullw. RT,RA,RB (OE=0 Rc=1)|mullwo RT,RA,RB (OE=1 Rc=0)|mullwo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|235@22|Rc@31|P1
1130NAND X-formnand RA,RS,RB (Rc=0)|nand. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|476@21|Rc@31|P1
1131Negate XO-formneg RT,RA (OE=0 Rc=0)|neg. RT,RA (OE=0 Rc=1)|nego RT,RA (OE=1 Rc=0)|nego. RT,RA (OE=1 Rc=1)31@0|RT@6|RA@11|///@16|OE@21|104@22|Rc@31|P1
1132NOR X-formnor RA,RS,RB (Rc=0)|nor. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|124@21|Rc@31|P1
1133OR X-formor RA,RS,RB (Rc=0)|or. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|444@21|Rc@31|P1
1134OR with Complement X-formorc RA,RS,RB (Rc=0)|orc. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|412@21|Rc@31|P1
1135OR Immediate D-formori RA,RS,UI|nop (RA=0 RS=0 UI=0)24@0|RS@6|RA@11|UI@16|P1
1136OR Immediate Shifted D-formoris RA,RS,UI25@0|RS@6|RA@11|UI@16|P1
1137Rotate Left Word Immediate then Mask Insert M-formrlwimi RA,RS,SH,MB,ME (Rc=0)|rlwimi. RA,RS,SH,MB,ME (Rc=1)20@0|RS@6|RA@11|SH@16|MB@21|ME@26|Rc@31|P1
1138Rotate Left Word Immediate then AND with Mask M-formrlwinm RA,RS,SH,MB,ME (Rc=0)|rlwinm. RA,RS,SH,MB,ME (Rc=1)21@0|RS@6|RA@11|SH@16|MB@21|ME@26|Rc@31|P1
1139Rotate Left Word then AND with Mask M-formrlwnm RA,RS,RB,MB,ME (Rc=0)|rlwnm. RA,RS,RB,MB,ME (Rc=1)23@0|RS@6|RA@11|RB@16|MB@21|ME@26|Rc@31|P1
1140Shift Left Word X-formslw RA,RS,RB (Rc=0)|slw. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|24@21|Rc@31|P1
1141Shift Right Algebraic Word X-formsraw RA,RS,RB (Rc=0)|sraw. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|792@21|Rc@31|P1
1142Shift Right Algebraic Word Immediate X-formsrawi RA,RS,SH (Rc=0)|srawi. RA,RS,SH (Rc=1)31@0|RS@6|RA@11|SH@16|824@21|Rc@31|P1
1143Shift Right Word X-formsrw RA,RS,RB (Rc=0)|srw. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|536@21|Rc@31|P1
1144Store Byte D-formstb RS,D(RA)38@0|RS@6|RA@11|D@16|P1
1145Store Byte with Update D-formstbu RS,D(RA)39@0|RS@6|RA@11|D@16|P1
1146Store Byte with Update Indexed X-formstbux RS,RA,RB31@0|RS@6|RA@11|RB@16|247@21|/@31|P1
1147Store Byte Indexed X-formstbx RS,RA,RB31@0|RS@6|RA@11|RB@16|215@21|/@31|P1
1148Store Floating-Point Double D-formstfd FRS,D(RA)54@0|FRS@6|RA@11|D@16|P1
1149Store Floating-Point Double with Update D-formstfdu FRS,D(RA)55@0|FRS@6|RA@11|D@16|P1
1150Store Floating-Point Double with Update Indexed X-formstfdux FRS,RA,RB31@0|FRS@6|RA@11|RB@16|759@21|/@31|P1
1151Store Floating-Point Double Indexed X-formstfdx FRS,RA,RB31@0|FRS@6|RA@11|RB@16|727@21|/@31|P1
1152Store Floating-Point Single D-formstfs FRS,D(RA)52@0|FRS@6|RA@11|D@16|P1
1153Store Floating-Point Single with Update D-formstfsu FRS,D(RA)53@0|FRS@6|RA@11|D@16|P1
1154Store Floating-Point Single with Update Indexed X-formstfsux FRS,RA,RB31@0|FRS@6|RA@11|RB@16|695@21|/@31|P1
1155Store Floating-Point Single Indexed X-formstfsx FRS,RA,RB31@0|FRS@6|RA@11|RB@16|663@21|/@31|P1
1156Store Halfword D-formsth RS,D(RA)44@0|RS@6|RA@11|D@16|P1
1157Store Halfword Byte-Reverse Indexed X-formsthbrx RS,RA,RB31@0|RS@6|RA@11|RB@16|918@21|/@31|P1
1158Store Halfword with Update D-formsthu RS,D(RA)45@0|RS@6|RA@11|D@16|P1
1159Store Halfword with Update Indexed X-formsthux RS,RA,RB31@0|RS@6|RA@11|RB@16|439@21|/@31|P1
1160Store Halfword Indexed X-formsthx RS,RA,RB31@0|RS@6|RA@11|RB@16|407@21|/@31|P1
1161Store Multiple Word D-formstmw RS,D(RA)47@0|RS@6|RA@11|D@16|P1
1162Store String Word Immediate X-formstswi RS,RA,NB31@0|RS@6|RA@11|NB@16|725@21|/@31|P1
1163Store String Word Indexed X-formstswx RS,RA,RB31@0|RS@6|RA@11|RB@16|661@21|/@31|P1
1164Store Word D-formstw RS,D(RA)36@0|RS@6|RA@11|D@16|P1
1165Store Word Byte-Reverse Indexed X-formstwbrx RS,RA,RB31@0|RS@6|RA@11|RB@16|662@21|/@31|P1
1166Store Word with Update D-formstwu RS,D(RA)37@0|RS@6|RA@11|D@16|P1
1167Store Word with Update Indexed X-formstwux RS,RA,RB31@0|RS@6|RA@11|RB@16|183@21|/@31|P1
1168Store Word Indexed X-formstwx RS,RA,RB31@0|RS@6|RA@11|RB@16|151@21|/@31|P1
1169Subtract From Carrying XO-formsubfc RT,RA,RB (OE=0 Rc=0)|subfc. RT,RA,RB (OE=0 Rc=1)|subfco RT,RA,RB (OE=1 Rc=0)|subfco. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|8@22|Rc@31|P1
1170Subtract From Extended XO-formsubfe RT,RA,RB (OE=0 Rc=0)|subfe. RT,RA,RB (OE=0 Rc=1)|subfeo RT,RA,RB (OE=1 Rc=0)|subfeo. RT,RA,RB (OE=1 Rc=1)31@0|RT@6|RA@11|RB@16|OE@21|136@22|Rc@31|P1
1171Subtract From Immediate Carrying D-formsubfic RT,RA,SI8@0|RT@6|RA@11|SI@16|P1
1172Subtract From Minus One Extended XO-formsubfme RT,RA (OE=0 Rc=0)|subfme. RT,RA (OE=0 Rc=1)|subfmeo RT,RA (OE=1 Rc=0)|subfmeo. RT,RA (OE=1 Rc=1)31@0|RT@6|RA@11|///@16|OE@21|232@22|Rc@31|P1
1173Subtract From Zero Extended XO-formsubfze RT,RA (OE=0 Rc=0)|subfze. RT,RA (OE=0 Rc=1)|subfzeo RT,RA (OE=1 Rc=0)|subfzeo. RT,RA (OE=1 Rc=1)31@0|RT@6|RA@11|///@16|OE@21|200@22|Rc@31|P1
1174Synchronize X-formsync L,SC31@0|//@6|L@8|///@11|SC@14|///@16|598@21|/@31|P1
1175TLB Invalidate Entry X-formtlbie RB,RS,RIC,PRS,R31@0|RS@6|/@11|RIC@12|PRS@14|R@15|RB@16|306@21|/@31|P1
1176Trap Word X-formtw TO,RA,RB31@0|TO@6|RA@11|RB@16|4@21|/@31|P1
1177Trap Word Immediate D-formtwi TO,RA,SI3@0|TO@6|RA@11|SI@16|P1
1178XOR X-formxor RA,RS,RB (Rc=0)|xor. RA,RS,RB (Rc=1)31@0|RS@6|RA@11|RB@16|316@21|Rc@31|P1
1179XOR Immediate D-formxori RA,RS,UI26@0|RS@6|RA@11|UI@16|P1
1180XOR Immediate Shifted D-formxoris RA,RS,UI27@0|RS@6|RA@11|UI@16|P1